Coremmc performance workaround #352
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jlaitine
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jlaitine
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mpfs_sendcmd() shall not wait for data lines ready before sending commands to the card. This prevents mmcsd driver to poll card busy status prior to next activity after a write operation.
4bit bus width support and FIC0 clock is 125MHz VR register fifo depth bitfields 5:4 instead of 3:2
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FIC0 definition added into Kconfig |
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Also the 4bit capability is checked from VR register instead of reported the support blindly |
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Summary
For Flat build poll lines_busy loop only short time at once and sleep for one system tick between checks if still busy.
Bus width and Fiq0 clock fixed.
Impact
This workaround is needed because coremmc does not have Transfer Completed interrupt, but the BUSY state shall be read from status register by polling. Just running in busy loop would cause very high cpuload by thread using the write operation of coremmc.