Review Request: Rough Implementation of LBR on Memtrace

SConstruct

@@ -31,7 +31,7 @@ def buildSim(cppFlags, dir, type, pgo=None):
     #env['CXX'] = 'g++ -flto -flto-report -fuse-linker-plugin'
     #env['CC'] = 'gcc -flto'
     env['CC'] = 'gcc7'
-    env['CXX'] = 'g++-7'
+    env['CXX'] = 'g++'
     #env["LINKFLAGS"] = " -O3 -finline "
     if useIcc:
         env['CC'] = 'icc'
@@ -122,7 +122,7 @@ def buildSim(cppFlags, dir, type, pgo=None):
     ##env["CPPFLAGS"] += " -DDEBUG=1"
 
     # Be a Warning Nazi? (recommended)
-    env["CPPFLAGS"] += " -Werror "
+    # env["CPPFLAGS"] += " -Werror "
     env["CPPFLAGS"] += " -Wno-unused-function "
     env["CPPFLAGS"] += " -Wno-int-in-bool-context "
 

source.sh

@@ -0,0 +1,4 @@
+export PINPATH=/home/takh/tools/pin-3.11
+export XEDPATH=~/git-repos/xed
+export LD_LIBRARY_PATH=$XEDPATH/kits/xed-install-base-2019-11-27-lin-x86-64/lib/
+export DRIOPATH=/home/takh/git-repos/dynamorio/

src/cache_arrays.cpp

@@ -44,12 +44,16 @@ void SetAssocArray::initStats(AggregateStat* parentStat) {
     objStats->init("array", "Cache array stats");
     profPrefHit.init("prefHits", "Cache line hits that were previously prefetched");
     objStats->append(&profPrefHit);
-    profPrefEarlyMiss.init("prefEarlyMiss", "Prefetched cache lines that were never used or fetched too early so they were already evicted from the cache");
+    profPrefEarlyMiss.init("prefEarlyMiss", "Prefetched cache lines that were never used or fetched too early so they were already evicted from the cache before 400 cycles from startCycle");
     objStats->append(&profPrefEarlyMiss);
+    profPrefNeverUsed.init("prefNeverUsed", "Prefetched cache lines that were never used or fetched too early so they were already evicted from the cache after 400 cycles from startCycle");
+    objStats->append(&profPrefNeverUsed);
     profPrefLateMiss.init("prefLateMiss", "Prefetched cache lines that were fetched too late and were still in flight");
     objStats->append(&profPrefLateMiss);
     profPrefLateTotalCycles.init("prefTotalLateCyc", "Total cycles lost waiting on late prefetches");
     objStats->append(&profPrefLateTotalCycles);
+    profPrefLateSavedCycles.init("profPrefLateSavedCycles", "Total cycles saved waiting on late prefetches");
+    objStats->append(&profPrefLateSavedCycles);
     profPrefSavedCycles.init("prefSavedCyc", "Total cycles saved by hitting a prefetched line (also if late)");
     objStats->append(&profPrefSavedCycles);
 
@@ -148,6 +152,7 @@ int32_t SetAssocArray::lookup(const Address lineAddr, const MemReq* req, bool up
                     profPrefLateMiss.inc();
                     profPrefLateTotalCycles.inc(*availCycle - req->cycle);
                     profPrefSavedCycles.inc(req->cycle - array[id].startCycle);
+                    profPrefLateSavedCycles.inc(req->cycle - array[id].startCycle);
                     if (isHWPrefetch(req)) {
                         profPrefHitPref.inc();
                     }
@@ -173,6 +178,13 @@ int32_t SetAssocArray::lookup(const Address lineAddr, const MemReq* req, bool up
         profPrefNotInCache.inc();
     }
 
+#ifdef LOG_L1I_MISS_LBR
+    if(req->core_lbr)
+    {
+        req->core_lbr->log_event(req->pc,lineAddr);
+    }
+#endif
+
 #ifdef MONITOR_MISS_PCS
     //Gather Load PC miss stats
     if (MONITORED_PCS && isDemandLoad(req)) {
@@ -227,7 +239,16 @@ void SetAssocArray::postinsert(const Address lineAddr, const MemReq* req, uint32
     }
 
     if(array[candidate].prefetch) {
-        profPrefEarlyMiss.inc();
+
+        if(array[candidate].startCycle + 400 > req->cycle)
+        {
+            profPrefEarlyMiss.inc();
+        }
+        else
+        {
+            profPrefNeverUsed.inc();
+        }
+
         if (isHWPrefetch(req)) {
             profPrefReplacePref.inc();
         }

src/cache_arrays.h

@@ -30,7 +30,9 @@
 #include "stats.h"
 #include "g_std/g_unordered_map.h"
 #include "g_std/g_multimap.h"
-//#define MONITOR_MISS_PCS //Uncomment to enable monitoring of cache misses
+#define MONITOR_MISS_PCS //Uncomment to enable monitoring of cache misses
+
+#define LOG_L1I_MISS_LBR
 
 struct AddrCycle {
     Address addr;   // block address
@@ -78,7 +80,7 @@ class SetAssocArray : public CacheArray {
         uint32_t setMask;
 
 #ifdef MONITOR_MISS_PCS
-        static const uint32_t MONITORED_PCS = 10;
+        static const uint32_t MONITORED_PCS = 25;
         g_unordered_map<uint64_t, uint64_t> miss_pcs;
         g_unordered_map<uint64_t, uint64_t> hit_pcs;
         g_unordered_map<uint64_t, uint64_t> late_addr;
@@ -97,8 +99,10 @@ class SetAssocArray : public CacheArray {
 
         Counter profPrefHit;
         Counter profPrefEarlyMiss;
+        Counter profPrefNeverUsed;
         Counter profPrefLateMiss;
         Counter profPrefLateTotalCycles;
+        Counter profPrefLateSavedCycles;
         Counter profPrefSavedCycles;
         Counter profPrefInaccurateOOO;
         Counter profHitDelayCycles;

src/filter_cache.h

@@ -31,6 +31,7 @@
 #include "galloc.h"
 #include "zsim.h"
 #include "ooo_core_recorder.h"
+#include "lbr.h"
 
 /* Extends Cache with an L0 direct-mapped cache, optimized to hell for hits
  *
@@ -128,16 +129,16 @@ class FilterCache : public Cache {
             parentStat->append(cacheStat);
         }
 
-        inline uint64_t load(Address vAddr, uint64_t curCycle, Address pc) {
+        inline uint64_t load(Address vAddr, uint64_t curCycle, Address pc, LBR_Stack *lbr=nullptr, bool no_update_timestamp=false, bool is_prefetch=false) {
             Address vLineAddr = vAddr >> lineBits;
             uint32_t idx = vLineAddr & setMask;
             uint64_t availCycle = filterArray[idx].availCycle; //read before, careful with ordering to avoid timing races
 
-            if (vLineAddr == filterArray[idx].rdAddr) {
+            if (vLineAddr == filterArray[idx].rdAddr && availCycle < curCycle) {
                 fGETSHit++;
-                return MAX(curCycle, availCycle);
+                return MAX(curCycle+accLat, availCycle);
             } else {
-                return replace(vLineAddr, idx, true, curCycle, pc);
+                return replace(vLineAddr, idx, true, curCycle, pc, lbr, no_update_timestamp,is_prefetch);
             }
         }
 
@@ -149,18 +150,31 @@ class FilterCache : public Cache {
                 fGETXHit++;
                 //NOTE: Stores don't modify availCycle; we'll catch matches in the core
                 //filterArray[idx].availCycle = curCycle; //do optimistic store-load forwarding
-                return MAX(curCycle, availCycle);
+                return MAX(curCycle+accLat, availCycle);
             } else {
                 return replace(vLineAddr, idx, false, curCycle, pc);
             }
         }
 
-        uint64_t replace(Address vLineAddr, uint32_t idx, bool isLoad, uint64_t curCycle, Address pc) {
+        uint64_t replace(Address vLineAddr, uint32_t idx, bool isLoad, uint64_t curCycle, Address pc, LBR_Stack *lbr=nullptr, bool no_update_timestamp=false, bool is_prefetch=false) {
           //assert(prefetchQueue.empty());
             Address pLineAddr = procMask | vLineAddr;
             MESIState dummyState = MESIState::I;
             futex_lock(&filterLock);
             MemReq req = {pc, pLineAddr, isLoad? GETS : GETX, 0, &dummyState, curCycle, &filterLock, dummyState, srcId, reqFlags};
+            if(lbr)
+            {
+                req.core_lbr = lbr;
+            }
+            else
+            {
+                req.core_lbr = nullptr;
+            }
+            req.no_update_timestamp = no_update_timestamp;
+            if(is_prefetch)
+            {
+                req.flags = req.flags| MemReq::SPECULATIVE;
+            }
             uint64_t respCycle  = access(req);
 
             //Due to the way we do the locking, at this point the old address might be invalidated, but we have the new address guaranteed until we release the lock

src/lbr.h

@@ -0,0 +1,125 @@
+#ifndef LBR_H_
+#define LBR_H_
+
+#include <stdint.h>
+#include <deque>
+#include <sstream>
+#include <string>
+#include <fstream>
+#include <iostream>
+#include <set>
+#include <unordered_map>
+#include <string>
+
+#define ENABLE_LBR
+#define LBR_CAPACITY 32
+
+class LBREntry
+{
+private:
+    uint64_t _bbl_address;
+    uint64_t _cycles; /*elapsed core clocks since last update to the LBR stack*/
+public:
+    LBREntry(uint64_t bbl_address, uint64_t cycles)
+    {
+        _bbl_address = bbl_address;
+        _cycles = cycles;
+    }
+    std::string get_string()
+    {
+        std::ostringstream os;
+        os<<_bbl_address<<";"<<_cycles;
+        return os.str();
+    }
+};
+
+class LBR_Stack
+{
+private:
+    std::deque<LBREntry> _queue;
+    uint64_t last_cycle;
+    std::ofstream log_file;
+    std::ofstream full_log_file;
+    std::ofstream bbl_info_file;
+    std::ofstream self_modifying_bbl_info_file;
+    std::set<uint64_t> observed_bbls;
+    std::unordered_map<uint64_t,std::set<uint32_t>> bbl_size_difference_check;
+    uint64_t current_bbl_index;
+public:
+    LBR_Stack()
+    {
+        last_cycle = 0;
+        current_bbl_index = 0;
+        _queue.clear();
+    }
+    void set_log_file(const char *path_name)
+    {
+        log_file.open(path_name);
+    }
+    void set_full_log_file(const char *path_name)
+    {
+        full_log_file.open(path_name);
+    }
+    void set_bbl_info_file(const char *path_name)
+    {
+        bbl_info_file.open(path_name);
+        std::string tmp(path_name);
+        tmp+="-self-modifying";
+        self_modifying_bbl_info_file.open(tmp.c_str());
+    }
+    void push(uint64_t bbl_address=0, uint64_t cur_cycle=0, uint32_t instrs=0, uint32_t bytes=0)
+    {
+        uint64_t result = cur_cycle;
+        if(cur_cycle!=0)
+        {
+            assert(cur_cycle>=last_cycle);
+            result=cur_cycle-last_cycle;
+            last_cycle = cur_cycle;
+        }
+        if(full_log_file.is_open())full_log_file<<bbl_address<<","<<result<<std::endl;
+        LBREntry new_entry(bbl_address, result);
+        if(likely(_queue.size()==LBR_CAPACITY))
+        {
+            _queue.pop_front();
+        }
+        _queue.push_back(new_entry);
+        if(observed_bbls.find(bbl_address)==observed_bbls.end())
+        {
+            observed_bbls.insert(bbl_address);
+            if(bbl_info_file.is_open())bbl_info_file<<bbl_address<<","<<instrs<<","<<bytes<<std::endl;
+            bbl_size_difference_check[bbl_address]=std::set<uint32_t>();
+            bbl_size_difference_check[bbl_address].insert(instrs);
+        }
+        else if (bbl_size_difference_check[bbl_address].find(instrs)==bbl_size_difference_check[bbl_address].end())
+        {
+            bbl_size_difference_check[bbl_address].insert(instrs);
+            if(self_modifying_bbl_info_file.is_open())self_modifying_bbl_info_file<<bbl_address<<","<<instrs<<","<<bytes<<std::endl;
+        }
+        current_bbl_index+=1;
+    }
+    std::string get_string()
+    {
+        std::ostringstream os;
+        for(int i=_queue.size()-1; i>-1; i--)
+        {
+            os<<_queue[i].get_string()<<",";
+        }
+        return os.str();
+    }
+    void log_event(uint64_t pc,uint64_t miss_cl_address)
+    {
+        if(log_file.is_open())log_file<<miss_cl_address<<","<<pc<<","<<get_string()<<current_bbl_index-1<<std::endl;
+    }
+    ~LBR_Stack()
+    {
+        if(log_file.is_open())log_file.close();
+        if(full_log_file.is_open())full_log_file.close();
+        if(bbl_info_file.is_open())bbl_info_file.close();
+        observed_bbls.clear();
+        if(self_modifying_bbl_info_file.is_open())self_modifying_bbl_info_file.close();
+        for(auto it: bbl_size_difference_check)it.second.clear();
+        bbl_size_difference_check.clear();
+    }
+};
+
+#endif  // LBR_H_

src/memory_hierarchy.h

@@ -33,6 +33,7 @@
 #include "g_std/g_vector.h"
 #include "galloc.h"
 #include "locks.h"
+#include "lbr.h"
 
 /** TYPES **/
 
@@ -108,6 +109,9 @@ struct MemReq {
     //At that point PREFETCH is effectively set for the target cache insertion.
     //Use with the 'SPECULATIVE' flag above to separate from demand accesses and to prevent additional reactive prefetches
     uint32_t prefetch;
+
+    LBR_Stack * core_lbr;
+    bool no_update_timestamp;
 
     inline void set(Flag f) {flags |= f;}
     inline bool is (Flag f) const {return flags & f;}