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Review Request: Rough Implementation of LBR on Memtrace #8

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Review Request: Rough Implementation of LBR on Memtrace #8

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takhandipu
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Hello Professor Litz,
Can you have a look at my LBR implementation? You don't have to merge this pull request to the original memtrace branch, I just wanted to be double sure about the accuracy of our LBR implementation. Since the accuracy and speedup of our simulation depends on the accuracy of LBR, I would greatly appreciate if you could at least review the changes and see whether the LBR implementation makes sense. Thanks once again for your help.
Kind regards,
Tanvir Ahmed Khan.

takhandipu and others added 30 commits December 23, 2019 22:44
@takhandipu
clang zero latency icache consumes 85% less cycles
6f281b5
@takhandipu
LBR data is defined, but mechanism is not
3a5e8e0
Implemented LBR
d97aa92
Semantic bug fix
0db17e3
Checking whether we can pass LBR pointer via MemReq
3ce9dfb
LBR uses uint64_t instead of Address to ensure MemReq can use that
3690a2d
remove bits/stdc++.h from lbr.h
e002c68
Trying to fix MemReq plain old data type error
c2130ac
Trying to see whether ooo_filter_cache load can take lbr (by feault n…
ef7f0fd 
…ullptr)
Trying to see whether filter_cache load can take lbr (by feault nullptr)
4d8b751
Trying to see whether filter_cache replace and cache_arrays lookup ca…
1996ccf 
…n take lbr (by feault nullptr)
LBR logging for a cache_arrays miss is enabled
2e9c002
Tiny syntactic bug fiz
bebf08d
Enabling lbr logging for each L1i->load() misses
0917048
Minor semantic bug fiz
b932c7a
Minor implementation bug fix
6aabb32
l1i->load for ooo_core now includes program counter so that we can lo…
5b52963 
…g miss
Wrong path L1i fetch does not include LBR or PC logging, Have to talk…
2c5689b 
… with Professor Litz regarding that
LBR data for a given BBL is pushed even before calling ooo_core->bbl …
a77cec4 
…on it, again have to check with Professor Litz
added missed cache line address when logging LBR, I guess LBR impleme…
e6be05b 
…ntation is complete
forgot to add lbr.h in the previous commit, I guess LBR implementatio…
fbd76e1 
…n is complete
@takhandipu
LBR driven prefetch distance based prefetching implementation on zsim…
f7634af 
… is complete
@takhandipu
Syntax error fix
bd5aab4
@takhandipu
Syntax error fix
50829ab
@takhandipu
Syntax error fix
bb80432
@takhandipu
Syntax error fix
b500b9d
@takhandipu
Syntax error fix
39bed0b
@takhandipu
Trying to fix c++ map SIGFPE
11ad32c
@takhandipu
Trying to fix c++ map SIGFPE
fe83948
@takhandipu
Profile-guided prefetching now works inside zsim, however, the result…
7d83033 
…s are not so good yet
takhandipu and others added 30 commits February 28, 2020 15:30
@takhandipu
minor compile fix
f5e27cf
@takhandipu
Pulled Heiner's fix from cdf5a3c
e4726c8
@takhandipu
Pulled Heiner's fix from cdf5a3c
71991a1
@takhandipu
reverting back to original issuePrefetch
921b0e9
@takhandipu
L1i prefetch now uses issuePrefetch
bdd030a
@takhandipu
making isSW flag true for software prefetch
9a5773a
@takhandipu
Making prefetches skip 1 to see what is the resut
0e52c52
@takhandipu
Undoing previous commit which reduces the performance by 14%
9b28dea
@takhandipu
Defining MONITOR_MISS_PCS based on Heiner's suggestion
fae80ae
@takhandipu
monitoring top-25 missed PCs
95b7828
@takhandipu
Adding a new counter profPrefLateSavedCycles
21e8f8e
Modified context-sensitive prefetch to support variable sized context
77baa28
context size up to 8
a5593a3
Minor fix
1f85e8c
made isSW prefetch false to see the results of all different counters
45e7ceb
divided profPrefEarlyMiss counter into profPrefEarlyMiss and profPref…
67b6298 
…NeverUsed counters based on 400 cycle difference from req->cycle and candidate's startCycle
Added a new entry at the end of the LBR string to map it on to the dcfg
1a5f6cc
minor bug fix
a004e37
Changed context sensitive prefetch file description again
5991382
minor bug fix context sensitive prefetch
febc4d4
minor garbage collection
412a8c1
AsmDB n-next line prefetching sim parameter is added to simulate the …
9a45a0c 
…analysis
AsmDB miss-based next line prefetching is implemented, let's see whet…
ed7862e 
…her it runs or not
Figuring out verilator next line anomaly
04b7242
Trying to combine context and coalesce in a better way
eec8b6c
Added the false positive rate parameter on the context sensitive pref…
fd7fc0d 
…etch
@takhandipu
Replace repz's with nops
6d222ca
@takhandipu
repz's could be 4 bytes as well
bd1b17b
@takhandipu
Added new flag and support to print branch and unconditional-branch d…
f5f1059 
…ynamic cdf
@takhandipu
Uncondition branch means every other branch types except conditional …
d8abe76 
…branch
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@takhandipu