[ESI] BSP: variable sized reads and gearboxing read responses

frontends/PyCDE/integration_test/esitester.py

@@ -22,7 +22,7 @@
 # RUN: esi-cosim.py --source %t -- esitester cosim env dmatest
 
 import pycde
-from pycde import AppID, Clock, Module, Reset, generator
+from pycde import AppID, Clock, Module, Reset, generator, modparams
 from pycde.bsp import cosim
 from pycde.constructs import Counter, Reg, Wire
 from pycde.esi import CallService
@@ -58,60 +58,71 @@ def construct(ports):
     CallService.call(AppID("PrintfExample"), arg_chan, Bits(0))
 
 
-class ReadMem(Module):
-  """Module which reads host memory at a certain address as given by writes to
-  MMIO register 0x8. Stores the read value and responds to all MMIO reads with
-  the stored value."""
-
-  clk = Clock()
-  rst = Reset()
-
-  @generator
-  def construct(ports):
-    cmd_chan_wire = Wire(Channel(esi.MMIOReadWriteCmdType))
-    resp_ready_wire = Wire(Bits(1))
-    cmd, cmd_valid = cmd_chan_wire.unwrap(resp_ready_wire)
-    mmio_xact = cmd_valid & resp_ready_wire
-
-    read_loc_ce = mmio_xact & cmd.write & (cmd.offset == 0x8)
-    read_loc = Reg(UInt(64),
-                   clk=ports.clk,
-                   rst=ports.rst,
-                   rst_value=0,
-                   ce=read_loc_ce)
-    read_loc.assign(cmd.data.as_uint())
-
-    mem_data_ce = Wire(Bits(1))
-    mem_data = Reg(Bits(64),
-                   clk=ports.clk,
-                   rst=ports.rst,
-                   rst_value=0,
-                   ce=mem_data_ce)
-
-    response_data = mem_data
-    response_chan, response_ready = Channel(Bits(64)).wrap(
-        response_data, cmd_valid)
-    resp_ready_wire.assign(response_ready)
-
-    mmio_rw = esi.MMIO.read_write(appid=AppID("ReadMem"))
-    mmio_rw_cmd_chan = mmio_rw.unpack(data=response_chan)['cmd']
-    cmd_chan_wire.assign(mmio_rw_cmd_chan)
-
-    tag = Counter(8)(clk=ports.clk, rst=ports.rst, increment=mmio_xact)
-
-    hostmem_read_req, hostmem_read_req_ready = Channel(
-        esi.HostMem.ReadReqType).wrap({
-            "tag": tag.out,
-            "address": read_loc
-        }, read_loc_ce.reg(ports.clk, ports.rst))
-
-    hostmem_read_resp = esi.HostMem.read(appid=AppID("ReadMem_hostread"),
-                                         req=hostmem_read_req,
-                                         data_type=Bits(64))
-    hostmem_read_resp_data, hostmem_read_resp_valid = hostmem_read_resp.unwrap(
-        1)
-    mem_data.assign(hostmem_read_resp_data.data)
-    mem_data_ce.assign(hostmem_read_resp_valid)
+@modparams
+def ReadMem(width: int):
+
+  class ReadMem(Module):
+    """Module which reads host memory at a certain address as given by writes to
+    MMIO register 0x8. Stores the read value and responds to all MMIO reads with
+    the stored value."""
+
+    clk = Clock()
+    rst = Reset()
+
+    @generator
+    def construct(ports):
+      cmd_chan_wire = Wire(Channel(esi.MMIOReadWriteCmdType))
+      resp_ready_wire = Wire(Bits(1))
+      cmd, cmd_valid = cmd_chan_wire.unwrap(resp_ready_wire)
+      mmio_xact = cmd_valid & resp_ready_wire
+
+      read_loc_ce = mmio_xact & cmd.write & (cmd.offset == 0x8)
+      read_loc = Reg(UInt(64),
+                     clk=ports.clk,
+                     rst=ports.rst,
+                     rst_value=0,
+                     ce=read_loc_ce,
+                     name="read_loc")
+      read_loc.assign(cmd.data.as_uint())
+
+      mem_data_ce = Wire(Bits(1))
+      mem_data = Reg(Bits(width),
+                     clk=ports.clk,
+                     rst=ports.rst,
+                     rst_value=0,
+                     ce=mem_data_ce,
+                     name="mem_data")
+
+      response_data = mem_data.as_bits(64)
+      response_chan, response_ready = Channel(Bits(64)).wrap(
+          response_data, cmd_valid)
+      resp_ready_wire.assign(response_ready)
+
+      mmio_rw = esi.MMIO.read_write(appid=AppID("ReadMem"))
+      mmio_rw_cmd_chan = mmio_rw.unpack(data=response_chan)['cmd']
+      cmd_chan_wire.assign(mmio_rw_cmd_chan)
+
+      tag = Counter(8)(clk=ports.clk,
+                       rst=ports.rst,
+                       clear=Bits(1)(0),
+                       increment=mmio_xact)
+
+      # Ignoring the ready signal isn't safe, but for cosim it's probably fine.
+      hostmem_read_req, hostmem_read_req_ready = Channel(
+          esi.HostMem.ReadReqType).wrap({
+              "tag": tag.out,
+              "address": read_loc
+          }, read_loc_ce.reg(ports.clk, ports.rst))
+
+      hostmem_read_resp = esi.HostMem.read(appid=AppID("ReadMem_hostread"),
+                                           req=hostmem_read_req,
+                                           data_type=mem_data.type)
+      hostmem_read_resp_data, hostmem_read_resp_valid = hostmem_read_resp.unwrap(
+          1)
+      mem_data.assign(hostmem_read_resp_data.data)
+      mem_data_ce.assign(hostmem_read_resp_valid)
+
+  return ReadMem
 
 
 class WriteMem(Module):
@@ -144,10 +155,14 @@ def construct(ports):
     mmio_rw_cmd_chan = mmio_rw.unpack(data=response_chan)['cmd']
     cmd_chan_wire.assign(mmio_rw_cmd_chan)
 
-    tag = Counter(8)(clk=ports.clk, rst=ports.rst, increment=mmio_xact)
+    tag = Counter(8)(clk=ports.clk,
+                     rst=ports.rst,
+                     clear=Bits(1)(0),
+                     increment=mmio_xact)
 
     cycle_counter = Counter(64)(clk=ports.clk,
                                 rst=ports.rst,
+                                clear=Bits(1)(0),
                                 increment=Bits(1)(1))
 
     hostmem_write_req, _ = esi.HostMem.wrap_write_req(
@@ -167,7 +182,10 @@ class EsiTesterTop(Module):
   @generator
   def construct(ports):
     PrintfExample(clk=ports.clk, rst=ports.rst)
-    ReadMem(clk=ports.clk, rst=ports.rst)
+    # Once I get read muxing working, enable all three.
+    # ReadMem(32)(clk=ports.clk, rst=ports.rst)
+    # ReadMem(64)(clk=ports.clk, rst=ports.rst)
+    ReadMem(96)(clk=ports.clk, rst=ports.rst)
     WriteMem(clk=ports.clk, rst=ports.rst)