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Add support for Xilinx zcu102 board rev1.1 #2117
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Current demo effect: Then the board stopped and could not continue. What might have happened? |
Would you be willing to set up UART+TSI-based bringup instead-of/in-addition-to SDBOOT? We don't really use SDBOOT anymore because it is difficult to debug. The nexysvideo and arty100t boards have UART+TSI based bringup. UART-TSI loads the binary onto the prototype over a standard USB-UART cable, and maintains FESVR for the prototype as well. |
@Jerryy959 can you describe what you are trying to do with these FPGA boards? Specifically: a) Do you require SD-card based bringup? I'm inclined to remove this entirely.... its nearly impossible to test and debug, and adds significant complexity to the entire process. |
Thanks for reply! @jerryz123 My ultimate goal is to launch Rocket + Linux on my board using the newest branch. To answer your question:
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…lliance/rocket-chip-fpga-shells#29 in chipsalliance/rocket-chip-fpga-shells.
…h supports pmod sd boot.
…rt h-ext, memory interface generator.
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I can try to modify your work into a simpler system that uses USB-UART-TSI-based bringup. This system is much more robust, but slower. It is the same mechanism used in the arty100t and nexysvideo boards. One downside of this approach is that it takes up the USB-UART of the board. You'll need a second PMOD-USB-UART to expose the target's UART console output, such that you can interact with the target. The other downside is that loading binaries over UART is slow. With Linux, it may take a few minutes. |
This PR implements support for the Xilinx zcu102 FPGA version of the code on the latest main branch, with testing performed on the Xilinx zcu102 rev1.1 to boot BootRom (using Pmod SD card).
And this PR also implements FPGA-shell for zcu102: chipsalliance/rocket-chip-fpga-shells#29
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as the base branch?changelog:<topic>
label?changelog:
label?.conda-lock.yml
file if you updated the conda requirements file?Please Backport
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- Run FPGA-based E2E testingci:local-fpga-buildbitstream-deploy
- Build local FPGA bitstreams for platforms that are releasedci:disable
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