- Title : Integrated Circuit Design Laboratory (ICLAB)
- Semester : Spring 2024
- Professor : Chen-Yi, Lee
- Registered numbers : 127
- Withdrawals : 38
- Average : 78.92 (Excluding withdrawals)
- Process : U18
- Simulation : VCS
- Synthesis : Design Compiler
- APR : Innovus
- Total Score : 94.19 (100%)
- Rank : 2 / 89
- Best code x 2 🏆
- No.1 x 2
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- No.6 x 1
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| Lab | Content | Design | Demo | Rank | Score | Pass Rate | Weight |
|---|---|---|---|---|---|---|---|
| Lab01 | Cell Based Design Methodology + Verilog Combinational Circuit Programming | Code Calculator | 1st | 6/114 | 98.68 | 89.76% | 5% |
| Lab02 | Finite State Machine + Verilog Sequential Circuit Programming | Enigma Machine | 1st | 24/109 | 93.67 | 85.83% | 5% |
| Lab03 | Verification & Simulation + Verilog Test Bench Programming | AXI-SPI DataBridge | 1st | NA | 100.0 | 75.59% | 5% |
| Lab04 | Sequential Circuit Design II (STA + Pipeline) + Designware IP | Convolution Neural Network | 1st | 23/95 | 93.05 | 74.80% | 5% |
| Lab05 | Memory & Coding Style (Memory Compiler + SuperLint) | Matrix convolution, max pooling and transposed convolution | 1st | 5/75 | 98.40 | 59.06% | 5% |
| Lab06 | Synthesis Methodology (Design Compiler + IP Design) + Soft IP | Huffman Code Operation | 1st | 1/99 | 100.0 | 77.95% | 5% |
| Lab07 | Timing: Cross Clock Domain with JasperGold + Synthesis Static Time Analysis | Matrix Multiplication with Clock Domain Crossing | 1st | 12/95 | 99.42 | 74.80% | 5% |
| Lab08 | System Verilog (Design) | Tea House (Design) | 1st | 4/93 | 99.03 | 73.23% | 5% |
| Lab09 | System Verilog II (Verification) | Tea House (Verification) | 1st | 5/72 | 99.44 | 56.69% | 5% |
| Lab10 | System Verilog (Formal Verification) | Formal Verification | 1st | NA | 100.0 | 76.38% | 3% |
| Lab11 | Power: Low Power Design with Sequential Equivalency Checking | Siamese Neural Network | 1st | 21/86 | 93.02 | 67.72% | 5% |
| Lab12 | APR I : From RTL to GDSII | Matrix convolution, max pooling and transposed convolution | 1st | 9/56 | 97.14 | 68.50% | 5% |
| Lab13 | APR II: IR-Drop Analysis | Train Tour APR II | 1st | NA | 100.0 | 68.50% | 5% |
| OT | Online Test | Infix to prefix convertor and prefix evaluation | 2nd | NA | 50.00 | 2.36% | 5% |
| MP | Midterm Project | Maze Router Accelerator | 1st | 1/87 | 100.0 | 68.50% | 8% |
| FP | Final Project | Single core CPU | 1st | 75/86 | 74.19 | 67.72% | 8% |
| ME | Midterm Exam (Mainly focus on front-end design) | - | - | 15 | 87.50 | - | 8% |
| FE | Final Exam (Mainly focus on back-end design) | - | - | 25 | 89.50 | - | 8% |