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[snippy] Illegal instruction during initialization by splats #158

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merged 1 commit into from
Feb 14, 2025
Merged

[snippy] Illegal instruction during initialization by splats #158

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12 changes: 0 additions & 12 deletions llvm/tools/llvm-snippy/lib/Target/RISCV/RVVUnitConfig.h
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Original file line number Diff line number Diff line change
Expand Up @@ -105,13 +105,6 @@ struct RVVConfiguration final {

void print(raw_ostream &OS) const;
void dump() const;

bool operator==(const RVVConfiguration &Other) const {
return LMUL == Other.LMUL && SEW == Other.SEW &&
MaskAgnostic == Other.MaskAgnostic &&
TailAgnostic == Other.TailAgnostic && VXRM == Other.VXRM &&
VxsatEnable == Other.VxsatEnable;
}
};

inline static bool isLegalSEW(unsigned SEW) {
Expand Down Expand Up @@ -217,11 +210,6 @@ struct RVVConfigurationInfo final {
struct VLVM {
unsigned VL;
APInt VM;

bool operator==(const VLVM &Other) const {
return VL == Other.VL && VM.getBitWidth() == Other.VM.getBitWidth() &&
VM == Other.VM;
}
};

static RVVConfigurationInfo
Expand Down
15 changes: 2 additions & 13 deletions llvm/tools/llvm-snippy/lib/Target/RISCV/Target.cpp
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Expand Up @@ -1270,13 +1270,7 @@ class SnippyRISCVTarget final : public SnippyTarget {
auto [RVVConfig, VLVM] =
constructRVVModeWithVMReset(RISCVII::VLMUL::LMUL_1, VLen, SEW, TA, MA);
const RVVModeInfo NewRVVMode{VLVM, RVVConfig, MBB};

const auto &RGC =
ProgCtx.getTargetContext().getImpl<RISCVGeneratorContext>();

if (!RGC.hasActiveRVVMode(MBB) || RGC.getActiveRVVMode(MBB) != NewRVVMode) {
generateRVVModeUpdate(IGC, InstrInfo, NewRVVMode);
}
generateRVVModeUpdate(IGC, InstrInfo, NewRVVMode);

// Initialize registers before taking a branch
// V0 is the mask register, skip it.
Expand Down Expand Up @@ -3322,12 +3316,7 @@ void SnippyRISCVTarget::rvvUnsafeWriteValueUsingXReg(
auto [RVVConfig, VLVM] =
constructRVVModeWithVMReset(RISCVII::VLMUL::LMUL_1, VL, SEW, TA, MA);
const RVVModeInfo NewRVVMode{VLVM, RVVConfig, MBB};
const auto &RGC = ProgCtx.getTargetContext().getImpl<RISCVGeneratorContext>();

// We might already have needed RVVMode
if (!RGC.hasActiveRVVMode(MBB) || RGC.getActiveRVVMode(MBB) != NewRVVMode) {
generateRVVModeUpdate(IGC, InstrInfo, NewRVVMode);
}
generateRVVModeUpdate(IGC, InstrInfo, NewRVVMode);

// Use non-reserved reg as scratch.
auto &RI = State.getRegInfo();
Expand Down
9 changes: 0 additions & 9 deletions llvm/tools/llvm-snippy/lib/Target/RISCV/TargetGenContext.h
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Expand Up @@ -30,15 +30,6 @@ struct RVVModeInfo {
RVVModeInfo(RVVConfigurationInfo::VLVM RVV_VLVM,
const RVVConfiguration &RVVCfg, const MachineBasicBlock &MBB)
: VLVM{std::move(RVV_VLVM)}, Config{&RVVCfg}, MBBGuard{&MBB} {}

bool operator==(const RVVModeInfo &Other) const {
return VLVM == Other.VLVM && MBBGuard == Other.MBBGuard &&
((Config != nullptr && Other.Config != nullptr &&
*Config == *Other.Config) ||
(Config == nullptr && Other.Config == nullptr));
}

bool operator!=(const RVVModeInfo &Other) const { return !(*this == Other); }
};

struct VSETWeightOverrides {
Expand Down