Repositories list

• caliptra-rtl

  Public
  HW Design Collateral for Caliptra RoT IP

  SystemVerilog

  •

  Apache License 2.0

  •44•82•81•14•Updated Jan 31, 2025Jan 31, 2025

• Cores-VeeR-EL2

  Public
  VeeR EL2 Core

  fpgaprocessorriscv+ 11rtlrisc-vopen-source-hardwarefusesocverilatorriscv32western-digital+ 4

  SystemVerilog

  •

  Apache License 2.0

  •76•259•20•7•Updated Jan 31, 2025Jan 31, 2025

• caliptra-sw

  Public
  Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

  Rust

  •

  Apache License 2.0

  •47•100•113•58•Updated Jan 31, 2025Jan 31, 2025

• t1

  Public
  Scala

  •

  Apache License 2.0

  •24•130•17•27•Updated Jan 31, 2025Jan 31, 2025

• synlig

  Public
  SystemVerilog synthesis tool

  Verilog

  •

  Apache License 2.0

  •23•177•69•10•Updated Jan 31, 2025Jan 31, 2025

• sv-tests-results

  Public
  Output of the sv-tests runs.

  HTML

  •2•5•0•0•Updated Jan 31, 2025Jan 31, 2025

• chips-alliance-website

  Public
  SCSS

  •

  MIT License

  •5•3•9•8•Updated Jan 31, 2025Jan 31, 2025

• caliptra-ss

  Public
  HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

  securityrotocp+ 3root-of-trustcaliptraopencomputeproject

  SystemVerilog

  •

  Apache License 2.0

  •5•11•17•6•Updated Jan 31, 2025Jan 31, 2025

• Caliptra

  Public
  Caliptra IP and firmware for integrated Root of Trust block

  Apache License 2.0

  •38•252•24•3•Updated Jan 31, 2025Jan 31, 2025

• caliptra-dpe

  Public
  High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs

  Rust

  •

  Apache License 2.0

  •22•15•11•7•Updated Jan 30, 2025Jan 30, 2025

• sv-tests

  Public
  Test suite designed to check compliance with the SystemVerilog standard.

  rtlverilogsystemverilog+ 3hdlcompliance-testingsymbiflow

  SystemVerilog

  •

  ISC License

  •75•306•46•34•Updated Jan 30, 2025Jan 30, 2025

• chisel-interface

  Public
  The 'missing header' for Chisel

  Scala

  •1•18•0•0•Updated Jan 30, 2025Jan 30, 2025

• caliptra-mcu-sw

  Public
  Caliptra MCU Software

  Rust

  •

  Apache License 2.0

  •1•9•7•4•Updated Jan 30, 2025Jan 30, 2025

• adams-bridge

  Public
  Post-Quantum Cryptography IP Core (Crystals-Dilithium)

  cryptographydigital-signaturelattice+ 2pqcml-dsa-87

  SystemVerilog

  •

  Apache License 2.0

  •2•13•8•1•Updated Jan 30, 2025Jan 30, 2025

• chisel

  Public
  Chisel: A Modern Hardware Design Language

  chip-generatorchiselrtl+ 4chisel3firrtlscalaverilog

  Scala

  •

  Apache License 2.0

  •613•4.1k•313•171•Updated Jan 30, 2025Jan 30, 2025

• rocket-chip

  Public
  Rocket Chip Generator

  chiselscalarocket-chip+ 3chip-generatorriscvrtl

  Scala

  •

  Other

  •1.1k•3.3k•234•63•Updated Jan 30, 2025Jan 30, 2025

• chisel-template

  Public template
  A template project for beginning new Chisel work

  Scala

  •

  The Unlicense

  •189•611•12•2•Updated Jan 30, 2025Jan 30, 2025

• i3c-core

  Public
  SystemVerilog

  •

  Apache License 2.0

  •3•12•11•0•Updated Jan 29, 2025Jan 29, 2025

• firtool-resolver

  Public
  Scala

  •1•2•0•1•Updated Jan 29, 2025Jan 29, 2025

• verible

  Public
  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

  productivityanalysisstyle-linter+ 14language-server-protocolsyntax-treelexeryaccsystemveriloghacktoberfestlsp-server+ 7

  C++

  •

  Other

  •221•1.4k•485•21•Updated Jan 29, 2025Jan 29, 2025

• firrtl-spec

  Public
  The specification for the FIRRTL language

  TeX

  •28•51•25•16•Updated Jan 28, 2025Jan 28, 2025

• chisel-nix

  Public
  Nix template for the chisel-based industrial designing flows.

  Nix

  •3•34•0•2•Updated Jan 27, 2025Jan 27, 2025

• synlig-logs

  Public
  SystemVerilog

  •0•0•0•0•Updated Jan 27, 2025Jan 27, 2025

• rvdecoderdb

  Public
  The Scala parser to parse riscv/riscv-opcodes generate

  Scala

  •3•13•0•1•Updated Jan 26, 2025Jan 26, 2025

• veer-el2-dashboard

  Public
  HTML

  •1•0•0•0•Updated Jan 22, 2025Jan 22, 2025

• rocket-pcb

  Public
  PCB libraries and templates for rocket-chip based FPGA/ASIC designs

  Verilog

  •

  Apache License 2.0

  •2•7•0•1•Updated Jan 22, 2025Jan 22, 2025

• rocket-pcblib

  Public
  Apache License 2.0

  •0•1•0•0•Updated Jan 22, 2025Jan 22, 2025

• verible-formatter-action

  Public
  SystemVerilog

  •

  Apache License 2.0

  •8•9•3•0•Updated Jan 21, 2025Jan 21, 2025

• rocket-chip-inclusive-cache

  Public
  An RTL generator for a last-level shared inclusive TileLink cache controller

  Scala

  •

  Apache License 2.0

  •20•15•7•4•Updated Jan 17, 2025Jan 17, 2025

• verilator

  Public
  Verilator open-source SystemVerilog simulator and lint system

  C++

  •

  GNU Lesser General Public License v3.0

  •632•35•0•1•Updated Jan 16, 2025Jan 16, 2025