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add X-IF 1.0 #284

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add X-IF 1.0 #284

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4cd1a8d
Core-V eXtension Interface (CV-X-IF) integration (#277)
FrancescoDeMalde-synthara Feb 27, 2025
9046348
minor fixes (#283)
davideschiavone Feb 27, 2025
2814470
minor fix again
davideschiavone Feb 27, 2025
73ba222
merge main
davideschiavone Mar 17, 2025
e8e7967
Changes to make the X_if addition compatible with the golden version …
cairo-caplan Mar 17, 2025
3bc1261
Fix remaining sec inconsistency regarding the X-IF addition (#291)
cairo-caplan Mar 25, 2025
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44 changes: 42 additions & 2 deletions rtl/cve2_core.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,8 @@ module cve2_core import cve2_pkg::*; #(
parameter rv32m_e RV32M = RV32MFast,
parameter rv32b_e RV32B = RV32BNone,
parameter bit DbgTriggerEn = 1'b0,
parameter int unsigned DbgHwBreakNum = 1
parameter int unsigned DbgHwBreakNum = 1,
parameter bit XInterface = 1'b0
) (
// Clock and Reset
input logic clk_i,
Expand Down Expand Up @@ -52,6 +53,25 @@ module cve2_core import cve2_pkg::*; #(
input logic [31:0] data_rdata_i,
input logic data_err_i,

// Core-V Extension Interface (CV-X-IF)
// Issue Interface
output logic x_issue_valid_o,
input logic x_issue_ready_i,
output x_issue_req_t x_issue_req_o,
input x_issue_resp_t x_issue_resp_i,

// Register Interface
output x_register_t x_register_o,

// Commit Interface
output logic x_commit_valid_o,
output x_commit_t x_commit_o,

// Result Interface
input logic x_result_valid_i,
output logic x_result_ready_o,
input x_result_t x_result_i,

// Interrupt inputs
input logic irq_software_i,
input logic irq_timer_i,
Expand Down Expand Up @@ -355,7 +375,8 @@ module cve2_core import cve2_pkg::*; #(
cve2_id_stage #(
.RV32E (RV32E),
.RV32M (RV32M),
.RV32B (RV32B)
.RV32B (RV32B),
.XInterface (XInterface)
) id_stage_i (
.clk_i (clk_i),
.rst_ni(rst_ni),
Expand Down Expand Up @@ -439,6 +460,25 @@ module cve2_core import cve2_pkg::*; #(
.lsu_load_err_i (lsu_load_err),
.lsu_store_err_i(lsu_store_err),

// Core-V Extension Interface (CV-X-IF)
// Issue Interface
.x_issue_valid_o(x_issue_valid_o),
.x_issue_ready_i(x_issue_ready_i),
.x_issue_req_o(x_issue_req_o),
.x_issue_resp_i(x_issue_resp_i),

// Register Interface
.x_register_o(x_register_o),

// Commit Interface
.x_commit_valid_o(x_commit_valid_o),
.x_commit_o(x_commit_o),

// Result Interface
.x_result_valid_i(x_result_valid_i),
.x_result_ready_o(x_result_ready_o),
.x_result_i(x_result_i),

// Interrupt Signals
.csr_mstatus_mie_i(csr_mstatus_mie),
.irq_pending_i (irq_pending_o),
Expand Down
74 changes: 44 additions & 30 deletions rtl/cve2_decoder.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,8 @@
module cve2_decoder #(
parameter bit RV32E = 0,
parameter cve2_pkg::rv32m_e RV32M = cve2_pkg::RV32MFast,
parameter cve2_pkg::rv32b_e RV32B = cve2_pkg::RV32BNone
parameter cve2_pkg::rv32b_e RV32B = cve2_pkg::RV32BNone,
parameter bit XInterface = 1'b0
) (
input logic clk_i,
input logic rst_ni,
Expand Down Expand Up @@ -50,46 +51,50 @@ module cve2_decoder #(
output logic [31:0] zimm_rs1_type_o,

// register file
output cve2_pkg::rf_wd_sel_e rf_wdata_sel_o, // RF write data selection
output logic rf_we_o, // write enable for regfile
output logic [4:0] rf_raddr_a_o,
output logic [4:0] rf_raddr_b_o,
output logic [4:0] rf_waddr_o,
output logic rf_ren_a_o, // Instruction reads from RF addr A
output logic rf_ren_b_o, // Instruction reads from RF addr B
output logic [XInterface:0] rf_wdata_sel_o, // RF write data selection
output logic rf_we_o, // write enable for regfile
output logic [4:0] rf_raddr_a_o,
output logic [4:0] rf_raddr_b_o,
output logic [4:0] rf_waddr_o,
output logic rf_ren_a_o, // Instruction reads from RF addr A
output logic rf_ren_b_o, // Instruction reads from RF addr B

// ALU
output cve2_pkg::alu_op_e alu_operator_o, // ALU operation selection
output cve2_pkg::op_a_sel_e alu_op_a_mux_sel_o, // operand a selection: reg value, PC,
// immediate or zero
output cve2_pkg::op_b_sel_e alu_op_b_mux_sel_o, // operand b selection: reg value or
// immediate
output logic alu_multicycle_o, // ternary bitmanip instruction
output cve2_pkg::alu_op_e alu_operator_o, // ALU operation selection
output cve2_pkg::op_a_sel_e alu_op_a_mux_sel_o, // operand a selection: reg value, PC,
// immediate or zero
output cve2_pkg::op_b_sel_e alu_op_b_mux_sel_o, // operand b selection: reg value or
// immediate
output logic alu_multicycle_o, // ternary bitmanip instruction

// MULT & DIV
output logic mult_en_o, // perform integer multiplication
output logic div_en_o, // perform integer division or remainder
output logic mult_sel_o, // as above but static, for data muxes
output logic div_sel_o, // as above but static, for data muxes
output logic mult_en_o, // perform integer multiplication
output logic div_en_o, // perform integer division or remainder
output logic mult_sel_o, // as above but static, for data muxes
output logic div_sel_o, // as above but static, for data muxes

output cve2_pkg::md_op_e multdiv_operator_o,
output logic [1:0] multdiv_signed_mode_o,
output cve2_pkg::md_op_e multdiv_operator_o,
output logic [1:0] multdiv_signed_mode_o,

// CSRs
output logic csr_access_o, // access to CSR
output cve2_pkg::csr_op_e csr_op_o, // operation to perform on CSR
output logic csr_access_o, // access to CSR
output cve2_pkg::csr_op_e csr_op_o, // operation to perform on CSR

// LSU
output logic data_req_o, // start transaction to data memory
output logic data_we_o, // write enable
output logic [1:0] data_type_o, // size of transaction: byte, half
// word or word
output logic data_sign_extension_o, // sign extension for data read from
output logic data_req_o, // start transaction to data memory
output logic data_we_o, // write enable
output logic [1:0] data_type_o, // size of transaction: byte, half
// word or word
output logic data_sign_extension_o, // sign extension for data read from
// memory

// Core-V eXtension interface (CV-X-IF)
input cve2_pkg::readregflags_t x_issue_resp_register_read_i,
input cve2_pkg::writeregflags_t x_issue_resp_writeback_i,

// jump/branches
output logic jump_in_dec_o, // jump is being calculated in ALU
output logic branch_in_dec_o
output logic jump_in_dec_o, // jump is being calculated in ALU
output logic branch_in_dec_o
);

import cve2_pkg::*;
Expand Down Expand Up @@ -632,6 +637,15 @@ module cve2_decoder #(
end
default: begin
illegal_insn = 1'b1;

// CV-X-IF
if(XInterface) begin
rf_ren_a_o = x_issue_resp_register_read_i[0];
rf_ren_b_o = x_issue_resp_register_read_i[1];
rf_we = x_issue_resp_writeback_i;
rf_wdata_sel_o = RF_WD_COPROC;
end

end
endcase

Expand All @@ -646,7 +660,7 @@ module cve2_decoder #(
// insufficient privileges), or when accessing non-available registers in RV32E,
// these cases are not handled here
if (illegal_insn) begin
rf_we = 1'b0;
rf_we &= XInterface;
data_req_o = 1'b0;
data_we_o = 1'b0;
jump_in_dec_o = 1'b0;
Expand Down
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