@@ -418,12 +418,19 @@ module cve2_id_stage #(
418
418
419
419
// Register file write data mux
420
420
always_comb begin : rf_wdata_id_mux
421
- unique case (rf_wdata_sel)
422
- RF_WD_EX : rf_wdata_id_o = result_ex_i;
423
- RF_WD_CSR : rf_wdata_id_o = csr_rdata_i;
424
- RF_WD_COPROC : rf_wdata_id_o = x_result_i.data;
425
- default : rf_wdata_id_o = result_ex_i;
426
- endcase
421
+ if (XInterface)
422
+ unique case (rf_wdata_sel)
423
+ RF_WD_EX : rf_wdata_id_o = result_ex_i;
424
+ RF_WD_CSR : rf_wdata_id_o = csr_rdata_i;
425
+ RF_WD_COPROC : rf_wdata_id_o = x_result_i.data;
426
+ default : rf_wdata_id_o = result_ex_i;
427
+ endcase
428
+ else
429
+ unique case (rf_wdata_sel)
430
+ RF_WD_EX : rf_wdata_id_o = result_ex_i;
431
+ RF_WD_CSR : rf_wdata_id_o = csr_rdata_i;
432
+ default : rf_wdata_id_o = result_ex_i;
433
+ endcase
427
434
end
428
435
429
436
// ///////////
@@ -711,7 +718,6 @@ module cve2_id_stage #(
711
718
stall_branch = 1'b0 ;
712
719
stall_alu = 1'b0 ;
713
720
stall_coproc = 1'b0 ;
714
- stall_coproc = 1'b0 ;
715
721
branch_set_raw_d = 1'b0 ;
716
722
jump_set_raw = 1'b0 ;
717
723
perf_branch_o = 1'b0 ;
@@ -800,7 +806,7 @@ module cve2_id_stage #(
800
806
stall_multdiv = multdiv_en_dec;
801
807
stall_branch = branch_in_dec;
802
808
stall_jump = jump_in_dec;
803
- stall_coproc = illegal_insn_dec;
809
+ stall_coproc = XInterface & illegal_insn_dec;
804
810
end
805
811
end
806
812
0 commit comments