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‎.gitignore

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@@ -1,5 +1,6 @@
11
# Build output
22
build
3+
buildsim.log
34

45
# Common editor/IDE config and temporary files
56
.project
@@ -34,3 +35,9 @@ modelsim.ini
3435

3536
# This is generated by Xcelium when running DV simulations, even with WAVE=0
3637
/dv/uvm/core_cve2/waves.shm
38+
39+
# This is generated by the sequential equivalent checking
40+
/scripts/sec/golden.src
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/scripts/sec/revised.src
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/scripts/sec/reports
43+
/scripts/sec/ref_design

‎CONTRIBUTING.md

+14-6
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@@ -1,18 +1,26 @@
11
# Contributing
2-
Contributors are encouraged to be a [member](https://www.openhwgroup.org/membership/) of the
3-
OpenHW Group. New members are always welcome.
2+
New Contributors and new Members are always welcome!
3+
Although membership is not required, most Contributors are [members](https://openhwfoundation.org/membership/become-a-member/)
4+
of the OpenHW Foundation and participate in one or more of our [Projects](https://openhwfoundation.org/projects/).
5+
6+
## Contributor Agreement
7+
Contributors **must** be covered by the terms of the [Eclipse Contributor Agreement](https://www.eclipse.org/legal/ECA.php)
8+
(for individuals) **or** the [Eclipse Member Committer and Contributor Agreement](https://www.eclipse.org/legal/committer_process/EclipseMemberCommitterAgreement.pdf)
9+
(for employees of Member companies). The ECA/MCCA provides a legal
10+
framework for a Contributor's technical contributions to the OpenHW Foundation,
11+
including provisions for grant of copyright license and a Developer
12+
Certificate of Origin on contributions merged into OpenHW Foundation repositories.
413

514
## Getting Started
6-
The [OpenHW Work Flow](https://github.com/openhwgroup/programs/blob/5fa810bf16d25cf32c7eca58be084975bec38f96/TGs/verification-task-group/documents/presentations/OpenHWGroup_WorkFlow.pdf) document
7-
is required reading. You will find information about the implementation and usage of the CORE-V verification environments
8-
in the [Verification Strategy](https://docs.openhwgroup.org/projects/core-v-verif/en/latest/index.html).
15+
The [OpenHW Work Flow](https://github.com/openhwgroup/programs/blob/5fa810bf16d25cf32c7eca58be084975bec38f96/TGs/verification-task-group/documents/presentations/OpenHWGroup_WorkFlow.pdf)
16+
document is recommended reading.
917

1018
## The Mechanics
1119
1. From GitHub: [fork](https://help.github.com/articles/fork-a-repo/) the [cve2](https://github.com/openhwgroup/cve2) repository
1220
2. Clone repository: `git clone https://github.com/[your_github_username]/cve2`
1321
3. Create your feature branch: `git checkout -b <my_branch>.`<br> Please uniquify your branch name. See the [Git Cheats](https://github.com/openhwgroup/core-v-verif/blob/master/GitCheats.md)
1422
for a useful nominclature.
1523
4. Make your edits...
16-
5. Commit your changes: `git commit -m 'Add some feature' -s`<br>; `-s` or `--sign-off` is engouraged, but not required.
24+
5. Commit your changes: `git commit -m 'Add some feature' -s`
1725
6. Push feature branch: `git push origin <my_branch>`
1826
7. From GitHub: submit a pull request

‎doc/02_user/integration.rst

+4-7
Original file line numberDiff line numberDiff line change
@@ -19,9 +19,7 @@ Instantiation Template
1919
.RV32E ( 0 ),
2020
.RV32M ( cve2_pkg::RV32MFast ),
2121
.RndCnstLfsrSeed ( cve2_pkg::RndCnstLfsrSeedDefault ),
22-
.RndCnstLfsrPerm ( cve2_pkg::RndCnstLfsrPermDefault ),
23-
.DmHaltAddr ( 32'h1A110800 ),
24-
.DmExceptionAddr ( 32'h1A110808 )
22+
.RndCnstLfsrPerm ( cve2_pkg::RndCnstLfsrPermDefault )
2523
) u_top (
2624
// Clock and reset
2725
.clk_i (),
@@ -65,6 +63,9 @@ Instantiation Template
6563
6664
// Debug interface
6765
.debug_req_i (),
66+
.debug_halted_o (),
67+
.dm_halt_addr_i (),
68+
.dm_exception_addr_i (),
6869
.crash_dump_o (),
6970
7071
// Special control signals
@@ -93,10 +94,6 @@ Parameters
9394
| | | | "cve2_pkg::RV32MFast": 3-4 cycle multiplier, iterative divider |
9495
| | | | "cve2_pkg::RV32MSingleCycle": 1-2 cycle multiplier, iterative divider |
9596
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
96-
| ``DmHaltAddr`` | int | 0x1A110800 | Address to jump to when entering Debug Mode |
97-
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
98-
| ``DmExceptionAddr`` | int | 0x1A110808 | Address to jump to when an exception occurs while in Debug Mode |
99-
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
10097

10198
Any parameter marked *EXPERIMENTAL* when enabled is not verified to the same standard as the rest of the Ibex core.
10299

‎doc/03_reference/debug.rst

+14-19
Original file line numberDiff line numberDiff line change
@@ -3,12 +3,12 @@
33
Debug Support
44
=============
55

6-
Ibex offers support for execution-based debug according to the `RISC-V Debug Specification <https://riscv.org/specifications/debug-specification/>`_, version 0.13.
6+
CVE2 offers support for execution-based debug according to the `RISC-V Debug Specification <https://riscv.org/specifications/debug-specification/>`_, version 0.13.
77

88

99
.. note::
1010

11-
Debug support in Ibex is only one of the components needed to build a System on Chip design with run-control debug support (think "the ability to attach GDB to a core over JTAG").
11+
Debug support in CVE2 is only one of the components needed to build a System on Chip design with run-control debug support (think "the ability to attach GDB to a core over JTAG").
1212
Additionally, a Debug Module and a Debug Transport Module, compliant with the RISC-V Debug Specification, are needed.
1313

1414
A supported open source implementation of these building blocks can be found in the `RISC-V Debug Support for PULP Cores IP block <https://github.com/pulp-platform/riscv-dbg/>`_.
@@ -18,29 +18,24 @@ Ibex offers support for execution-based debug according to the `RISC-V Debug Spe
1818
Interface
1919
---------
2020

21-
+-----------------+-----------+-----------------------------+
22-
| Signal | Direction | Description |
23-
+=================+===========+=============================+
24-
| ``debug_req_i`` | input | Request to enter Debug Mode |
25-
+-----------------+-----------+-----------------------------+
21+
+----------------------------------+---------------------+--------------------------------------------------------------------------------------+
22+
| Signal | Direction | Description |
23+
+==================================+=====================+======================================================================================+
24+
| ``debug_req_i`` | input | Request to enter Debug Mode |
25+
+----------------------------------+---------------------+--------------------------------------------------------------------------------------+
26+
| ``debug_halted_o`` | output | Asserted if core enters Debug Mode |
27+
+----------------------------------+---------------------+--------------------------------------------------------------------------------------+
28+
| ``dm_halt_addr_i`` | input | Address to jump to when entering Debug Mode (default 0x1A110800) |
29+
+----------------------------------+---------------------+--------------------------------------------------------------------------------------+
30+
| ``dm_exception_addr_i`` | input | Address to jump to when an exception occurs while in Debug Mode (default 0x1A110808) |
31+
+----------------------------------+---------------------+--------------------------------------------------------------------------------------+
2632

2733
``debug_req_i`` is the "debug interrupt", issued by the debug module when the core should enter Debug Mode.
2834

29-
Parameters
30-
----------
31-
32-
+---------------------+-----------------------------------------------------------------+
33-
| Parameter | Description |
34-
+=====================+=================================================================+
35-
| ``DmHaltAddr`` | Address to jump to when entering Debug Mode |
36-
+---------------------+-----------------------------------------------------------------+
37-
| ``DmExceptionAddr`` | Address to jump to when an exception occurs while in Debug Mode |
38-
+---------------------+-----------------------------------------------------------------+
39-
4035
Core Debug Registers
4136
--------------------
4237

43-
Ibex implements four core debug registers, namely :ref:`csr-dcsr`, :ref:`csr-dpc`, and two debug scratch registers.
38+
CVE2 implements four core debug registers, namely :ref:`csr-dcsr`, :ref:`csr-dpc`, and two debug scratch registers.
4439
Debug trigger registers are available. See :ref:`csr-tselect`, :ref:`csr-tdata1` and :ref:`csr-tdata2` for details.
4540
All those registers are accessible from Debug Mode only.
4641
If software tries to access them without the core being in Debug Mode, an illegal instruction exception is triggered.

‎dv/riscv_compliance/rtl/cve2_riscv_compliance.sv

+7-5
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,12 @@
11
// Copyright lowRISC contributors.
2+
// Copyright 2025 OpenHW Group.
23
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
34
// SPDX-License-Identifier: Apache-2.0
45

56
/**
6-
* Ibex simulation to run the RISC-V compliance test on
7+
* CVE2 simulation to run the RISC-V compliance test on
78
*
8-
* This is a toplevel wrapper for Ibex with helpers to run the RISC-V compliance
9+
* This is a toplevel wrapper for CVE2 with helpers to run the RISC-V compliance
910
* test. It is designed for Verilator, but should equally work for other
1011
* simulators (if the top-level clk and rst ports are replaced with a generated
1112
* clock).
@@ -121,9 +122,7 @@ module cve2_riscv_compliance (
121122
.ICache (ICache ),
122123
.ICacheECC (ICacheECC ),
123124
.SecureIbex (SecureIbex ),
124-
.ICacheScramble (ICacheScramble ),
125-
.DmHaltAddr (32'h00000000 ),
126-
.DmExceptionAddr (32'h00000000 )
125+
.ICacheScramble (ICacheScramble )
127126
) u_top (
128127
.clk_i (clk_sys ),
129128
.rst_ni (rst_sys_n ),
@@ -168,6 +167,9 @@ module cve2_riscv_compliance (
168167
.scramble_req_o ( ),
169168

170169
.debug_req_i ('b0 ),
170+
.debug_halted_o ( ),
171+
.dm_halt_addr_i (32'h00000000 ),
172+
.dm_exception_addr_i (32'h00000000 ),
171173
.crash_dump_o ( ),
172174
.double_fault_seen_o ( ),
173175

‎rtl/cve2_core.sv

+17-10
Original file line numberDiff line numberDiff line change
@@ -10,21 +10,19 @@
1010
`include "prim_assert.sv"
1111

1212
/**
13-
* Top level module of the ibex RISC-V core
13+
* Top level module of the CVE2 RISC-V core
1414
*/
1515
module cve2_core import cve2_pkg::*; #(
1616
parameter bit PMPEnable = 1'b0,
1717
parameter int unsigned PMPGranularity = 0,
1818
parameter int unsigned PMPNumRegions = 4,
19-
parameter int unsigned MHPMCounterNum = 0,
19+
parameter int unsigned MHPMCounterNum = 10,
2020
parameter int unsigned MHPMCounterWidth = 40,
2121
parameter bit RV32E = 1'b0,
2222
parameter rv32m_e RV32M = RV32MFast,
2323
parameter rv32b_e RV32B = RV32BNone,
2424
parameter bit DbgTriggerEn = 1'b0,
2525
parameter int unsigned DbgHwBreakNum = 1,
26-
parameter int unsigned DmHaltAddr = 32'h1A110800,
27-
parameter int unsigned DmExceptionAddr = 32'h1A110808,
2826
parameter bit XInterface = 1'b0
2927
) (
3028
// Clock and Reset
@@ -84,6 +82,9 @@ module cve2_core import cve2_pkg::*; #(
8482

8583
// Debug Interface
8684
input logic debug_req_i,
85+
output logic debug_halted_o,
86+
input logic [31:0] dm_halt_addr_i,
87+
input logic [31:0] dm_exception_addr_i,
8788
output crash_dump_t crash_dump_o,
8889
// SEC_CM: EXCEPTION.CTRL_FLOW.LOCAL_ESC
8990
// SEC_CM: EXCEPTION.CTRL_FLOW.GLOBAL_ESC
@@ -304,10 +305,7 @@ module cve2_core import cve2_pkg::*; #(
304305
// IF stage //
305306
//////////////
306307

307-
cve2_if_stage #(
308-
.DmHaltAddr (DmHaltAddr),
309-
.DmExceptionAddr (DmExceptionAddr)
310-
) if_stage_i (
308+
cve2_if_stage if_stage_i (
311309
.clk_i (clk_i),
312310
.rst_ni(rst_ni),
313311

@@ -353,6 +351,10 @@ module cve2_core import cve2_pkg::*; #(
353351
.csr_mtvec_i (csr_mtvec), // trap-vector base address
354352
.csr_mtvec_init_o(csr_mtvec_init),
355353

354+
// debug signals
355+
.dm_halt_addr_i (dm_halt_addr_i),
356+
.dm_exception_addr_i (dm_exception_addr_i),
357+
356358
// pipeline stalls
357359
.id_in_ready_i(id_in_ready),
358360

@@ -363,7 +365,7 @@ module cve2_core import cve2_pkg::*; #(
363365
// available
364366
assign perf_iside_wait = id_in_ready & ~instr_valid_id;
365367

366-
// For non secure Ibex only the bottom bit of fetch enable is considered
368+
// For non secure CVE2 only the bottom bit of fetch enable is considered
367369
assign instr_req_gated = instr_req_int;
368370

369371
//////////////
@@ -650,6 +652,11 @@ module cve2_core import cve2_pkg::*; #(
650652
assign crash_dump_o.last_data_addr = lsu_addr_last;
651653
assign crash_dump_o.exception_addr = csr_mepc;
652654

655+
///////////////////////
656+
// Debug output //
657+
///////////////////////
658+
659+
assign debug_halted_o = debug_mode;
653660

654661
// Explict INC_ASSERT block to avoid unused signal lint warnings were asserts are not included
655662
`ifdef INC_ASSERT
@@ -1034,7 +1041,7 @@ module cve2_core import cve2_pkg::*; #(
10341041

10351042
assign rvfi_stage_order_d = rvfi_stage_order[0] + 64'd1;
10361043

1037-
// For interrupts and debug Ibex will take the relevant trap as soon as whatever instruction in ID
1044+
// For interrupts and debug CVE2 will take the relevant trap as soon as whatever instruction in ID
10381045
// finishes or immediately if the ID stage is empty. The rvfi_ext interface provides the DV
10391046
// environment with information about the irq/debug_req/nmi state that applies to a particular
10401047
// instruction.

‎rtl/cve2_if_stage.sv

+8-6
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
// Copyright lowRISC contributors.
22
// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.
3+
// Copyright 2025 OpenHW Group.
34
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
45
// SPDX-License-Identifier: Apache-2.0
56

@@ -12,10 +13,7 @@
1213

1314
`include "prim_assert.sv"
1415

15-
module cve2_if_stage import cve2_pkg::*; #(
16-
parameter int unsigned DmHaltAddr = 32'h1A110800,
17-
parameter int unsigned DmExceptionAddr = 32'h1A110808
18-
) (
16+
module cve2_if_stage import cve2_pkg::*; (
1917
input logic clk_i,
2018
input logic rst_ni,
2119

@@ -68,6 +66,10 @@ module cve2_if_stage import cve2_pkg::*; #(
6866
input logic [31:0] csr_mtvec_i, // base PC to jump to on exception
6967
output logic csr_mtvec_init_o, // tell CS regfile to init mtvec
7068

69+
// debug signals
70+
input logic [31:0] dm_halt_addr_i, // default 32'h1A110800
71+
input logic [31:0] dm_exception_addr_i, // default 32'h1A110808
72+
7173
// pipeline stall
7274
input logic id_in_ready_i, // ID stage is ready for new instr
7375

@@ -123,8 +125,8 @@ module cve2_if_stage import cve2_pkg::*; #(
123125
unique case (exc_pc_mux_i)
124126
EXC_PC_EXC: exc_pc = { csr_mtvec_i[31:8], 8'h00 };
125127
EXC_PC_IRQ: exc_pc = { csr_mtvec_i[31:8], irq_id[5:0], 2'b00 };
126-
EXC_PC_DBD: exc_pc = DmHaltAddr;
127-
EXC_PC_DBG_EXC: exc_pc = DmExceptionAddr;
128+
EXC_PC_DBD: exc_pc = dm_halt_addr_i;
129+
EXC_PC_DBG_EXC: exc_pc = dm_exception_addr_i;
128130
default: exc_pc = { csr_mtvec_i[31:8], 8'h00 };
129131
endcase
130132
end

‎rtl/cve2_top.sv

+10-7
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
// Copyright lowRISC contributors.
22
// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.
3+
// Copyright 2025 OpenHW Group.
34
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
45
// SPDX-License-Identifier: Apache-2.0
56

@@ -10,15 +11,13 @@
1011
`include "prim_assert.sv"
1112

1213
/**
13-
* Top level module of the ibex RISC-V core
14+
* Top level module of the CVE2 RISC-V core
1415
*/
1516
module cve2_top import cve2_pkg::*; #(
16-
parameter int unsigned MHPMCounterNum = 0,
17+
parameter int unsigned MHPMCounterNum = 10,
1718
parameter int unsigned MHPMCounterWidth = 40,
1819
parameter bit RV32E = 1'b0,
1920
parameter rv32m_e RV32M = RV32MFast,
20-
parameter int unsigned DmHaltAddr = 32'h1A110800,
21-
parameter int unsigned DmExceptionAddr = 32'h1A110808,
2221
parameter bit XInterface = 1'b0
2322
) (
2423
// Clock and Reset
@@ -78,6 +77,9 @@ module cve2_top import cve2_pkg::*; #(
7877

7978
// Debug Interface
8079
input logic debug_req_i,
80+
output logic debug_halted_o,
81+
input logic [31:0] dm_halt_addr_i,
82+
input logic [31:0] dm_exception_addr_i,
8183
output crash_dump_t crash_dump_o,
8284

8385
// RISC-V Formal Interface
@@ -127,7 +129,7 @@ module cve2_top import cve2_pkg::*; #(
127129
localparam int unsigned PMPNumRegions = 4;
128130

129131
// Trigger support
130-
localparam bit DbgTriggerEn = 1'b1;
132+
localparam bit DbgTriggerEn = 1'b1; // DEBUG_TRIGGER_EN in CVE4
131133
localparam int unsigned DbgHwBreakNum = 1;
132134

133135
// Bit manipulation extension
@@ -180,8 +182,6 @@ module cve2_top import cve2_pkg::*; #(
180182
.RV32B (RV32B),
181183
.DbgTriggerEn (DbgTriggerEn),
182184
.DbgHwBreakNum (DbgHwBreakNum),
183-
.DmHaltAddr (DmHaltAddr),
184-
.DmExceptionAddr (DmExceptionAddr),
185185
.XInterface (XInterface)
186186
) u_cve2_core (
187187
.clk_i(clk),
@@ -235,6 +235,9 @@ module cve2_top import cve2_pkg::*; #(
235235
.irq_pending_o(irq_pending),
236236

237237
.debug_req_i,
238+
.debug_halted_o,
239+
.dm_halt_addr_i,
240+
.dm_exception_addr_i,
238241
.crash_dump_o,
239242

240243
`ifdef RVFI

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