-
Notifications
You must be signed in to change notification settings - Fork 2
/
Copy pathMakefile
85 lines (70 loc) · 3.21 KB
/
Makefile
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
GHDL=ghdl
PRIMARY=top
VHDL_EXT=vhdl
LOG_FILE=build.log
ERR_STREAM=>> $(LOG_FILE) 2>> $(LOG_FILE)
MAKE_OPT=--no-print-directory
REDBOLD=\e[1;31m
BLUEBOLD=\e[1;36m
NC='\033[0m'
.PHONY:
all clean simulate synth route generate flash all_err stats error warning
all:
@$(MAKE) clean $(MAKE_OPT)
@$(MAKE) simulate $(MAKE_OPT) || $(MAKE) all_err $(MAKE_OPT)
@$(MAKE) synth $(MAKE_OPT)
@$(MAKE) route $(MAKE_OPT) || $(MAKE) all_err $(MAKE_OPT)
@$(MAKE) generate $(MAKE_OPT)
@$(MAKE) flash $(MAKE_OPT) && echo -en "$(BLUEBOLD)==== Done ====$(NC)\n"
-$(MAKE) svg $(MAKE_OPT)
clean:
@echo -en "$(BLUEBOLD)==== Cleaning... ====$(NC)\n"
rm -rf *.bin *.asc *.json *.cf $(LOG_FILE) && touch $(LOG_FILE)
simulate:
@echo -en "$(BLUEBOLD)==== Simulating... ====$(NC)\n"
$(GHDL) -a *.$(VHDL_EXT) $(ERR_STREAM)
synth: # Synthesize the design
@echo -en "$(BLUEBOLD)==== Synthesizing... ====$(NC)\n"
yosys -p '$(GHDL) $(PRIMARY); synth_ice40 -json $(PRIMARY).json' $(ERR_STREAM)
route: # P&R specifically for upduino
@echo -en "$(BLUEBOLD)==== Routing... ====$(NC)\n"
nextpnr-ice40 --up5k --package sg48 --pcf "$(PRIMARY).pcf" --asc "$(PRIMARY).asc" --json "$(PRIMARY).json" $(ERR_STREAM)
generate: # Generate bitstream
@echo -en "$(BLUEBOLD)==== Generating... ====$(NC)\n"
icepack "$(PRIMARY).asc" "$(PRIMARY).bin" $(ERR_STREAM)
flash: # Flash FPGA, may need to be run with sudo depending on user permissions
@echo -en "$(BLUEBOLD)==== Flashing... ====$(NC)\n"
sudo iceprog $(PRIMARY).bin | tee -a $(LOG_FILE)
all_err:
@echo -en "$(REDBOLD)"
@$(MAKE) error $(MAKE_OPT)
@echo -en $(NC)
@exit 1
stats: # Print out device usage stats from log files
@echo "///////////////// Statistics: /////////////////"
@echo "from $(LOG_FILE):"
-@cat -n $(LOG_FILE) | grep -A 9 "=== $(PRIMARY) ===" | grep -v "=== $(PRIMARY) ===" 2>/dev/null || true
@echo "--"
-@cat -n $(LOG_FILE) | grep -A 16 "Info: Device utilisation:" 2>/dev/null || true
error: # Print out errors from log files
@echo "///////////////// Error(s): /////////////////"
@echo "from $(LOG_FILE):"
-@cat -n $(LOG_FILE) | grep -v " 0 errors" | grep -C 1 -i "error" 2>/dev/null || true
-@cat -n $(LOG_FILE) | grep -C 3 -i ".$(VHDL_EXT)" 2>/dev/null || true
warning:
@echo "///////////////// Warning(s): /////////////////"
@echo "from $(LOG_FILE):"
@cat -n $(LOG_FILE) | grep -v " 0 warnings" | grep -C 1 -i "warning" 2>/dev/null || true
help:
@echo "run 'make' or 'make all' to synth, route, and flash code to the FPGA"
@echo "run 'make stats' to view usage stats about your last 'make all' if it was successful"
@echo "run 'make error' or 'make warning' to view errors and warnings about your last 'make all'"
@echo "run 'make clean' to delete build and log files that are generated by 'make all'"
@echo "run 'make simulate/synth/route/generate/flash' to run that specific cmd from 'make all'"
svg:
@$(MAKE) clean $(MAKE_OPT)
@$(MAKE) simulate $(MAKE_OPT) || $(MAKE) all_err $(MAKE_OPT)
@echo -en "$(BLUEBOLD)==== Drawing... ====$(NC)\n"
yosys -p "ghdl $(PRIMARY); prep -top $(PRIMARY); write_json svg.json" $(ERR_STREAM)
sed -i 's/"top": "00000000000000000000000000000001"/"top": 1/g' svg.json $(ERR_STREAM)
netlistsvg svg.json -o $(PRIMARY).svg $(ERR_STREAM)