Backport 25533 to earlgrey 1.0.0 #25669
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Squashed the contents of #25670 into this one as well. |
moidx
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Feb 5, 2025
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CHANGE AUTHORIZED: hw/ip/prim_xilinx/rtl/prim_xilinx_pkg.sv |
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CHANGE AUTHORIZED: hw/ip/prim_xilinx/rtl/prim_xilinx_pkg.sv |
Reduce BUILD file boilerplate by placing all memory map info in a single file. Use a separate Processor element for each map, so the InstData attribute can be used as a key to identify the memory to be updated. This construction also permits multiple memories to be spliced in a single call to updatemem, though that is not implemented in this commit. Adjust MMI dump to use a regex for mem type and a dictionary for each memory's parameters. For the mem type, some memories in the FPGA can consist of both RAMB36 and RAMB18 types, depending on the width of the array. The regex allows more flexible memory cell detection. Rev up the bitstream manifest schema to v3 so the memories contained in the MMI file are described. Add a function to collect MMI data from v2 cache entries and rewrite in the expected v3 format, with the MMI data in a single file. Finally, drop support for bitstream cache entries that do not contain a manifest. The tools to create a manifest have been in the repo for awhile, and as of this commit's creation, no such cache entries remain in the public cloud storage bucket. Signed-off-by: Alexander Williams <[email protected]> (cherry picked from commit 9e1ef80)
For earlgrey, export the flash info memory maps to the MMI file. Add
knowledge of these maps existing to the bitstream cache entries. The
flash info arrays are identified by a key in this format:
flash<FlashBank>_info<InfoType>
Add KEEP_HIERARCHY to the prim_ram_1p instances representing the flash
info arrays. This helps keep intelligible hierarchical paths to the
memories, so we can readily select the correct cells.
This lays groundwork for a future PR where we can splice these memories.
Signed-off-by: Alexander Williams <[email protected]>
(cherry picked from commit bf595b6)
Add a specialized ram_1p prim for the prim_xilinx library. This prim adds some prim_xilinx-specific parameters to enable selecting particular layouts for embedded memories. The intention is to have the top-level override the parameters with hierarchical assignment. This feature is intended for use with memories that are too wide to fit in updatemem's capabilities (where splicing is required). The flash info pages are one such type, since updatemem can only handle up to 64-bit wide items, and the info page array is 76 bits wide. Synthesis chooses the most efficient layout of the memories, but the layout is awkward for handling splices. Force earlgrey's flash info data and metadata into separate arrays for the FPGA. Signed-off-by: Alexander Williams <[email protected]> (cherry picked from commit 9776162)
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FYI, if you'd like to take this cherry-pick, know that I'm not authorized to merge pull requests on this branch. Someone with the powers will need to click the button. |
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Manually backport #25533 to earlgrey 1.0.0 branch.