Skip to content

[hw,ram,params] $ceil is not synthesizable, drop it... #7397

[hw,ram,params] $ceil is not synthesizable, drop it...

[hw,ram,params] $ceil is not synthesizable, drop it... #7397

Triggered via pull request March 14, 2025 20:18
Status Success
Total duration 5h 4m 43s
Artifacts 31

ci.yml

on: pull_request
Earl Grey for CW310 Hyperdebug  /  Build bitstream
1h 6m
Earl Grey for CW310 Hyperdebug / Build bitstream
Earl Grey for CW310  /  Build bitstream
1h 4m
Earl Grey for CW310 / Build bitstream
Earl Grey for CW340  /  Build bitstream
1h 24m
Earl Grey for CW340 / Build bitstream
Lint (slow)
11m 27s
Lint (slow)
Build documentation
4m 59s
Build documentation
Airgapped build
12m 5s
Airgapped build
Verible lint
1m 9s
Verible lint
Run OTBN smoke Test
2m 27s
Run OTBN smoke Test
Run OTBN crypto tests
3m 22s
Run OTBN crypto tests
Verilated English Breakfast
7m 8s
Verilated English Breakfast
Verilated Earl Grey
1h 13m
Verilated Earl Grey
CW305's Bitstream
23m 19s
CW305's Bitstream
Build Docker Containers
2m 28s
Build Docker Containers
Build and test software
17m 40s
Build and test software
Build and test Darjeeling software
3m 48s
Build and test Darjeeling software
QEMU smoketest
1m 58s
QEMU smoketest
Hyper310 ROM_EXT Tests  /  FPGA test
15m 31s
Hyper310 ROM_EXT Tests / FPGA test
CW310 SiVal Tests  /  FPGA test
26m 42s
CW310 SiVal Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
32m 39s
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 Manufacturing Tests  /  FPGA test
28m 41s
CW310 Manufacturing Tests / FPGA test
CW310 Test ROM Tests  /  FPGA test
3m 48s
CW310 Test ROM Tests / FPGA test
CW310 ROM Tests  /  FPGA test
41m 20s
CW310 ROM Tests / FPGA test
CW340 Test ROM Tests  /  FPGA test
3m 27s
CW340 Test ROM Tests / FPGA test
CW340 ROM Tests  /  FPGA test
49s
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
6m 18s
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
19m 23s
CW340 SiVal Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
5m 12s
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 Manufacturing Tests  /  FPGA test
43m 46s
CW340 Manufacturing Tests / FPGA test
Cache bitstreams to GCP
0s
Cache bitstreams to GCP
Verify FPGA jobs
25s
Verify FPGA jobs
Fit to window
Zoom out
Zoom in

Annotations

4 errors
Verilated English Breakfast
Process completed with exit code 1.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Process completed with exit code 1.
Build and test software
Process completed with exit code 1.

Artifacts

Produced during runtime
Name Size
chip_englishbreakfast_cw305
1.38 MB
execute_manuf_fpga_tests_cw310-targets
623 Bytes
execute_manuf_fpga_tests_cw310-test-results
59.3 KB
execute_manuf_fpga_tests_cw340-targets
594 Bytes
execute_manuf_fpga_tests_cw340-test-results
55.3 KB
execute_rom_ext_fpga_tests_cw310-targets
676 Bytes
execute_rom_ext_fpga_tests_cw310-test-results
63.7 KB
execute_rom_ext_fpga_tests_cw340-targets
441 Bytes
execute_rom_ext_fpga_tests_cw340-test-results
7.27 KB
execute_rom_fpga_tests_cw310-targets
1.73 KB
execute_rom_fpga_tests_cw310-test-results
45.2 KB
execute_rom_fpga_tests_cw340-targets
162 Bytes
execute_rom_fpga_tests_cw340-test-results
201 Bytes
execute_sival_fpga_tests_cw310-targets
784 Bytes
execute_sival_fpga_tests_cw310-test-results
37.5 KB
execute_sival_fpga_tests_cw340-targets
514 Bytes
execute_sival_fpga_tests_cw340-test-results
40.9 KB
execute_sival_rom_ext_fpga_tests_cw310-targets
2.27 KB
execute_sival_rom_ext_fpga_tests_cw310-test-results
194 KB
execute_sival_rom_ext_fpga_tests_cw340-targets
449 Bytes
execute_sival_rom_ext_fpga_tests_cw340-test-results
19.2 KB
execute_test_rom_fpga_tests_cw310-targets
326 Bytes
execute_test_rom_fpga_tests_cw310-test-results
3.25 KB
execute_test_rom_fpga_tests_cw340-targets
258 Bytes
execute_test_rom_fpga_tests_cw340-test-results
45.3 KB
partial-build-bin-chip_earlgrey_cw310
6.02 MB
partial-build-bin-chip_earlgrey_cw310_hyperdebug
5.99 MB
partial-build-bin-chip_earlgrey_cw340
10 MB
sw_build_test-test-results
246 KB
verilated_englishbreakfast
7.03 MB
verilator_earlgrey-test-results
9.19 KB