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GPIO straps verif #5673

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GPIO straps verif

GPIO straps verif #5673

Triggered via pull request February 7, 2025 16:23
@marcelocarvalhoLowRiscmarcelocarvalhoLowRisc
synchronize #25868
marcelocarvalhoLowRisc:gpio_straps_verif
Status Success
Total duration 1h 24m 1s
Artifacts 31

ci.yml

on: pull_request
Lint (quick)
3m 13s
Lint (quick)
Earl Grey for CW310 Hyperdebug  /  Build bitstream
1m 50s
Earl Grey for CW310 Hyperdebug / Build bitstream
Earl Grey for CW310  /  Build bitstream
1m 48s
Earl Grey for CW310 / Build bitstream
Earl Grey for CW340  /  Build bitstream
1m 45s
Earl Grey for CW340 / Build bitstream
Lint (slow)
11m 52s
Lint (slow)
Build documentation
5m 14s
Build documentation
Airgapped build
12m 17s
Airgapped build
Verible lint
1m 8s
Verible lint
Run OTBN smoke Test
2m 58s
Run OTBN smoke Test
Run OTBN crypto tests
3m 10s
Run OTBN crypto tests
Verilated English Breakfast
8m 24s
Verilated English Breakfast
Verilated Earl Grey
1h 20m
Verilated Earl Grey
CW305's Bitstream
28m 4s
CW305's Bitstream
Build Docker Containers
2m 48s
Build Docker Containers
Build and test software
16m 46s
Build and test software
QEMU smoketest
2m 5s
QEMU smoketest
Hyper310 ROM_EXT Tests  /  FPGA test
2m 39s
Hyper310 ROM_EXT Tests / FPGA test
CW310 SiVal Tests  /  FPGA test
2m 54s
CW310 SiVal Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
4m 55s
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 Manufacturing Tests  /  FPGA test
3m 3s
CW310 Manufacturing Tests / FPGA test
CW310 Test ROM Tests  /  FPGA test
2m 3s
CW310 Test ROM Tests / FPGA test
CW310 ROM Tests  /  FPGA test
3m 40s
CW310 ROM Tests / FPGA test
CW340 Test ROM Tests  /  FPGA test
2m 6s
CW340 Test ROM Tests / FPGA test
CW340 ROM Tests  /  FPGA test
56s
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
2m 26s
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
2m 23s
CW340 SiVal Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
2m 13s
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 Manufacturing Tests  /  FPGA test
2m 49s
CW340 Manufacturing Tests / FPGA test
Cache bitstreams to GCP
0s
Cache bitstreams to GCP
Verify FPGA jobs
25s
Verify FPGA jobs
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9 errors
Verilated English Breakfast
Process completed with exit code 1.
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Some target names have banned characters.
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Countermeasure check failed.
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Process completed with exit code 1.
Build and test software
Process completed with exit code 1.

Artifacts

Produced during runtime
Name Size
chip_englishbreakfast_cw305
1.37 MB
execute_manuf_fpga_tests_cw310-targets
623 Bytes
execute_manuf_fpga_tests_cw310-test-results
59.8 KB
execute_manuf_fpga_tests_cw340-targets
594 Bytes
execute_manuf_fpga_tests_cw340-test-results
54.6 KB
execute_rom_ext_fpga_tests_cw310-targets
598 Bytes
execute_rom_ext_fpga_tests_cw310-test-results
31.7 KB
execute_rom_ext_fpga_tests_cw340-targets
427 Bytes
execute_rom_ext_fpga_tests_cw340-test-results
7.06 KB
execute_rom_fpga_tests_cw310-targets
1.73 KB
execute_rom_fpga_tests_cw310-test-results
46 KB
execute_rom_fpga_tests_cw340-targets
162 Bytes
execute_rom_fpga_tests_cw340-test-results
201 Bytes
execute_sival_fpga_tests_cw310-targets
784 Bytes
execute_sival_fpga_tests_cw310-test-results
38.2 KB
execute_sival_fpga_tests_cw340-targets
507 Bytes
execute_sival_fpga_tests_cw340-test-results
40.4 KB
execute_sival_rom_ext_fpga_tests_cw310-targets
2.27 KB
execute_sival_rom_ext_fpga_tests_cw310-test-results
186 KB
execute_sival_rom_ext_fpga_tests_cw340-targets
449 Bytes
execute_sival_rom_ext_fpga_tests_cw340-test-results
19.7 KB
execute_test_rom_fpga_tests_cw310-targets
326 Bytes
execute_test_rom_fpga_tests_cw310-test-results
3.2 KB
execute_test_rom_fpga_tests_cw340-targets
258 Bytes
execute_test_rom_fpga_tests_cw340-test-results
44.3 KB
partial-build-bin-chip_earlgrey_cw310
5.99 MB
partial-build-bin-chip_earlgrey_cw310_hyperdebug
5.99 MB
partial-build-bin-chip_earlgrey_cw340
10.1 MB
sw_build_test-test-results
73.2 KB
verilated_englishbreakfast
7.03 MB
verilator_earlgrey-test-results
9.12 KB