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[Zk ext] V.1.0.0 Scalar cryptography extension implementation for the Ibex core #1480

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[Zk ext] V.1.0.0 Scalar cryptography extension implementation for the Ibex core #1480

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268bdaa
Zk: add support to the zkh extension
phthinh Nov 23, 2021
0e43b0e
Zk: add implementation for the zkh extension
phthinh Nov 23, 2021
033900c
Zk: add support for the aes instructions
phthinh Nov 24, 2021
dee7228
Zk: add the implementation for AES instructions
phthinh Nov 24, 2021
4a9472e
Zk: add the implementation for AES instructions
phthinh Nov 24, 2021
f95dab2
Zk: add support for decode the SM3/4 instructions.
phthinh Nov 24, 2021
45e7d2d
ZK: add the implementation of SM3/4 instructions
phthinh Nov 25, 2021
6df183a
ZK: add the implementation of SM3/4 instructions
phthinh Nov 25, 2021
06d9be9
Zk: add support for decode the ZBK instructions.
phthinh Nov 26, 2021
887d877
Zk: add the implementation of the Zbk(Zbkb, Zbkc, Zbkx) instructions.
phthinh Nov 26, 2021
e8967f8
ZK: small fixes for zip/unzip instructions
phthinh Nov 30, 2021
687250c
Merge branch 'lowRISC:master' into zk_ext
phthinh Dec 1, 2021
5f5eddb
add the Zk feature for Ibex configurations.
phthinh Dec 2, 2021
1ef9340
ZK: add --RV32Zk argument for Fusesoc.
phthinh Dec 2, 2021
6393a5d
ZK: edit rtl code style for veriblelint check.
phthinh Dec 2, 2021
c66cfbc
ZK: fix a define-style issue of RV32B in riscv_compliance test.
phthinh Dec 2, 2021
cd015f6
ZK: fix a define-style issue of RV32Zk.
phthinh Dec 2, 2021
9402788
Merge branch 'lowRISC:master' into zk_ext
phthinh Dec 2, 2021
f3d43d0
ZK: fix the rtl code style issues
phthinh Dec 3, 2021
3a1eb7c
ZK: stick to the macro name style rule, change RV32Zk -> RV32K.
phthinh Dec 3, 2021
a8ebc6f
Merge branch 'master' into zk_ext
phthinh Dec 7, 2021
4990ce7
ZK: fix some changes in rtl from upstream merging.
phthinh Dec 7, 2021
704eaf3
ZK: fix a line length style.
phthinh Dec 8, 2021
2204257
Merge branch 'master' into zk_ext
phthinh Jan 4, 2022
47f2dc9
fix lint errors
phthinh Jan 4, 2022
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Zk: add support for decode the SM3/4 instructions.
@phthinh
phthinh committed Nov 24, 2021

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commit f95dab2349221e69416e17488d4d5e4a952857b2
38 changes: 27 additions & 11 deletions rtl/ibex_decoder.sv
View file
Original file line number Diff line number Diff line change
@@ -394,6 +394,8 @@ module ibex_decoder #(
7'b000_0001, // sha256sum1
7'b000_0010, // sha256sig0
7'b000_0011: illegal_insn = (RV32Zk == RV32Zkn) ? 1'b0 : 1'b1; // sha256sig1
7'b000_1000, // sm3p0
7'b000_1001: illegal_insn = (RV32Zk == RV32Zks) ? 1'b0 : 1'b1; // sm3p1
default: illegal_insn = 1'b1;
endcase
end
@@ -457,8 +459,10 @@ module ibex_decoder #(
rf_we = 1'b1;
if ({instr[26], instr[13:12]} == {1'b1, 2'b01}) begin
illegal_insn = (RV32B != RV32BNone) ? 1'b0 : 1'b1; // cmix / cmov / fsl / fsr
end else if ({instr[29:28],instr[25], instr[14:12]} == {3'b101, 3'b000}) begin
end else if ({instr[29:28],instr[25], instr[14:12]} == {3'b10__1, 3'b000}) begin
illegal_insn = (RV32Zk == RV32Zkn) ? 1'b0 : 1'b1; // aes32ds / aes32dsm / aes32es / aes32esm
end else if ({instr[29:27],instr[25], instr[14:12]} == {4'b110_0, 3'b000}) begin
illegal_insn = (RV32Zk == RV32Zks) ? 1'b0 : 1'b1; // sm4ed / sm4ks
end else begin
unique case ({instr[31:25], instr[14:12]})
// RV32I ALU operations
@@ -881,12 +885,14 @@ module ibex_decoder #(
default: ;
endcase
end
5'b0_0010: begin // Zk, zkh
5'b0_0010: begin // Zk, zkh,zks
unique case (instr_alu[26:20])
7'b000_0000: if (RV32Zk == RV32Zkn) alu_operator_o = ZKN_SHA256SUM0; // sha256sum0
7'b000_0001: if (RV32Zk == RV32Zkn) alu_operator_o = ZKN_SHA256SUM1; // sha256sum1
7'b000_0010: if (RV32Zk == RV32Zkn) alu_operator_o = ZKN_SHA256SIG0; // sha256sig0
7'b000_0011: if (RV32Zk == RV32Zkn) alu_operator_o = ZKN_SHA256SIG1; // sha256sig1
7'b000_1000: if (RV32Zk == RV32Zks) alu_operator_o = ZKS_SM3P0; // sm3p0
7'b000_1001: if (RV32Zk == RV32Zks) alu_operator_o = ZKS_SM3P1; // sm3p1
default: alu_operator_o = ALU_SLL;
endcase
end
@@ -1075,24 +1081,34 @@ module ibex_decoder #(
{7'b010_1110, 3'b000}: if (RV32Zk == RV32Zkn) alu_operator_o = ZKN_SHA512SIG0H; // sha512_sig0h
{7'b010_1111, 3'b000}: if (RV32Zk == RV32Zkn) alu_operator_o = ZKN_SHA512SIG1H; // sha512_sig1h

// RV32Zk zkde
{7'b001_0001, 3'b000}: if (RV32Zk == RV32Zkn) alu_operator_o = ZKN_AES32ESB0; // aes32esb0
{7'b011_0001, 3'b000}: if (RV32Zk == RV32Zkn) alu_operator_o = ZKN_AES32ESB1; // aes32esb1
{7'b101_0001, 3'b000}: if (RV32Zk == RV32Zkn) alu_operator_o = ZKN_AES32ESB2; // aes32esb2
{7'b111_0001, 3'b000}: if (RV32Zk == RV32Zkn) alu_operator_o = ZKN_AES32ESB3; // aes32esb3
// RV32Zk zkned
{7'b001_0001, 3'b000}: if (RV32Zk == RV32Zkn) alu_operator_o = ZKN_AES32ESB0; // aes32esb0
{7'b011_0001, 3'b000}: if (RV32Zk == RV32Zkn) alu_operator_o = ZKN_AES32ESB1; // aes32esb1
{7'b101_0001, 3'b000}: if (RV32Zk == RV32Zkn) alu_operator_o = ZKN_AES32ESB2; // aes32esb2
{7'b111_0001, 3'b000}: if (RV32Zk == RV32Zkn) alu_operator_o = ZKN_AES32ESB3; // aes32esb3
{7'b001_0011, 3'b000}: if (RV32Zk == RV32Zkn) alu_operator_o = ZKN_AES32ESMB0; // aes32esmb0
{7'b011_0011, 3'b000}: if (RV32Zk == RV32Zkn) alu_operator_o = ZKN_AES32ESMB1; // aes32esmb1
{7'b101_0011, 3'b000}: if (RV32Zk == RV32Zkn) alu_operator_o = ZKN_AES32ESMB2; // aes32esmb2
{7'b111_0011, 3'b000}: if (RV32Zk == RV32Zkn) alu_operator_o = ZKN_AES32ESMB3; // aes32esmb3
{7'b001_0101, 3'b000}: if (RV32Zk == RV32Zkn) alu_operator_o = ZKN_AES32DSB0; // aes32dsb0
{7'b011_0101, 3'b000}: if (RV32Zk == RV32Zkn) alu_operator_o = ZKN_AES32DSB1; // aes32dsb1
{7'b101_0101, 3'b000}: if (RV32Zk == RV32Zkn) alu_operator_o = ZKN_AES32DSB2; // aes32dsb2
{7'b111_0101, 3'b000}: if (RV32Zk == RV32Zkn) alu_operator_o = ZKN_AES32DSB3; // aes32dsb3
{7'b001_0101, 3'b000}: if (RV32Zk == RV32Zkn) alu_operator_o = ZKN_AES32DSB0; // aes32dsb0
{7'b011_0101, 3'b000}: if (RV32Zk == RV32Zkn) alu_operator_o = ZKN_AES32DSB1; // aes32dsb1
{7'b101_0101, 3'b000}: if (RV32Zk == RV32Zkn) alu_operator_o = ZKN_AES32DSB2; // aes32dsb2
{7'b111_0101, 3'b000}: if (RV32Zk == RV32Zkn) alu_operator_o = ZKN_AES32DSB3; // aes32dsb3
{7'b001_0111, 3'b000}: if (RV32Zk == RV32Zkn) alu_operator_o = ZKN_AES32DSMB0; // aes32dsmb0
{7'b011_0111, 3'b000}: if (RV32Zk == RV32Zkn) alu_operator_o = ZKN_AES32DSMB1; // aes32dsmb1
{7'b101_0111, 3'b000}: if (RV32Zk == RV32Zkn) alu_operator_o = ZKN_AES32DSMB2; // aes32dsmb2
{7'b111_0111, 3'b000}: if (RV32Zk == RV32Zkn) alu_operator_o = ZKN_AES32DSMB3; // aes32dsmb3

// RV32Zk zks
{7'b001_1000, 3'b000}: if (RV32Zk == RV32Zks) alu_operator_o = ZKS_SM4EDB0; // sm4edb0
{7'b011_1000, 3'b000}: if (RV32Zk == RV32Zks) alu_operator_o = ZKS_SM4EDB1; // sm4edb1
{7'b101_1000, 3'b000}: if (RV32Zk == RV32Zks) alu_operator_o = ZKS_SM4EDB2; // sm4edb2
{7'b111_1000, 3'b000}: if (RV32Zk == RV32Zks) alu_operator_o = ZKS_SM4EDB3; // sm4edb3
{7'b001_1010, 3'b000}: if (RV32Zk == RV32Zks) alu_operator_o = ZKS_SM4KSB0; // sm4ksb0
{7'b011_1010, 3'b000}: if (RV32Zk == RV32Zks) alu_operator_o = ZKS_SM4KSB1; // sm4ksb1
{7'b101_1010, 3'b000}: if (RV32Zk == RV32Zks) alu_operator_o = ZKS_SM4KSB2; // sm4ksb2
{7'b111_1010, 3'b000}: if (RV32Zk == RV32Zks) alu_operator_o = ZKS_SM4KSB3; // sm4ksb3

// RV32M instructions, all use the same ALU operation
{7'b000_0001, 3'b000}: begin // mul
alu_operator_o = ALU_ADD;
14 changes: 13 additions & 1 deletion rtl/ibex_pkg.sv
View file
Original file line number Diff line number Diff line change
@@ -211,7 +211,19 @@ package ibex_pkg;
ZKN_AES32ESMB0,
ZKN_AES32ESMB1,
ZKN_AES32ESMB2,
ZKN_AES32ESMB3
ZKN_AES32ESMB3,

//Zks
ZKS_SM4EDB0,
ZKS_SM4EDB1,
ZKS_SM4EDB2,
ZKS_SM4EDB3,
ZKS_SM4KSB0,
ZKS_SM4KSB1,
ZKS_SM4KSB2,
ZKS_SM4KSB3,
ZKS_SM3P0,
ZKS_SM3P1
} alu_op_e;

typedef enum logic [1:0] {
2 changes: 1 addition & 1 deletion rtl/ibex_top.sv
View file
Original file line number Diff line number Diff line change
@@ -21,7 +21,7 @@ module ibex_top import ibex_pkg::*; #(
parameter bit RV32E = 1'b0,
parameter rv32m_e RV32M = RV32MFast,
parameter rv32b_e RV32B = RV32BNone,
parameter rv32zk_e RV32Zk = RV32Zkn,
parameter rv32zk_e RV32Zk = RV32Zks,
parameter regfile_e RegFile = RegFileFF,
parameter bit BranchTargetALU = 1'b0,
parameter bit WritebackStage = 1'b0,