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[TableGen] Replace some uses of make_range with methods that already return a range. NFC #123453

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Jan 18, 2025
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[TableGen] Replace some uses of make_range with methods that already return a range. NFC #123453

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17 changes: 7 additions & 10 deletions llvm/utils/TableGen/Common/CodeGenSchedule.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -979,8 +979,9 @@ unsigned CodeGenSchedModels::addSchedClass(const Record *ItinClassDef,
return SC.isKeyEqual(ItinClassDef, OperWrites, OperReads);
};

auto I = find_if(make_range(schedClassBegin(), schedClassEnd()), IsKeyEqual);
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I considered using schedClases() here but I would still need schedClassEnd() on the next line. The rest of this function already uses the SchedClasses member directly so I decided to just skip the accessor methods.

unsigned Idx = I == schedClassEnd() ? 0 : std::distance(schedClassBegin(), I);
auto I = find_if(SchedClasses, IsKeyEqual);
unsigned Idx =
I == SchedClasses.end() ? 0 : std::distance(SchedClasses.begin(), I);
if (Idx || SchedClasses[0].isKeyEqual(ItinClassDef, OperWrites, OperReads)) {
IdxVec PI;
std::set_union(SchedClasses[Idx].ProcIndices.begin(),
Expand Down Expand Up @@ -1103,8 +1104,7 @@ void CodeGenSchedModels::createInstRWClass(const Record *InstRWDef) {

// True if collectProcItins found anything.
bool CodeGenSchedModels::hasItineraries() const {
for (const CodeGenProcModel &PM :
make_range(procModelBegin(), procModelEnd()))
for (const CodeGenProcModel &PM : procModels())
if (PM.hasItineraries())
return true;
return false;
Expand All @@ -1129,8 +1129,7 @@ void CodeGenSchedModels::collectProcItins() {
const Record *ItinDef = ItinData->getValueAsDef("TheClass");
bool FoundClass = false;

for (const CodeGenSchedClass &SC :
make_range(schedClassBegin(), schedClassEnd())) {
for (const CodeGenSchedClass &SC : schedClasses()) {
// Multiple SchedClasses may share an itinerary. Update all of them.
if (SC.ItinClassDef == ItinDef) {
ProcModel.ItinDefList[SC.Index] = ItinData;
Expand Down Expand Up @@ -1420,8 +1419,7 @@ void PredTransitions::getIntersectingVariants(
if (AliasProcIdx && AliasProcIdx != TransVec[TransIdx].ProcIndex)
continue;
if (!Variants.empty()) {
const CodeGenProcModel &PM =
*(SchedModels.procModelBegin() + AliasProcIdx);
const CodeGenProcModel &PM = SchedModels.procModels()[AliasProcIdx];
PrintFatalError((*AI)->getLoc(),
"Multiple variants defined for processor " +
PM.ModelName +
Expand Down Expand Up @@ -1834,8 +1832,7 @@ void CodeGenSchedModels::collectProcResources() {
// Add any subtarget-specific SchedReadWrites that are directly associated
// with processor resources. Refer to the parent SchedClass's ProcIndices to
// determine which processors they apply to.
for (const CodeGenSchedClass &SC :
make_range(schedClassBegin(), schedClassEnd())) {
for (const CodeGenSchedClass &SC : schedClasses()) {
if (SC.ItinClassDef) {
collectItinProcResources(SC.ItinClassDef);
continue;
Expand Down
3 changes: 1 addition & 2 deletions llvm/utils/TableGen/SubtargetEmitter.cpp
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Expand Up @@ -1104,8 +1104,7 @@ void SubtargetEmitter::genSchedClassTables(const CodeGenProcModel &ProcModel,

// A Variant SchedClass has no resources of its own.
bool HasVariants = false;
for (const CodeGenSchedTransition &CGT :
make_range(SC.Transitions.begin(), SC.Transitions.end())) {
for (const CodeGenSchedTransition &CGT : SC.Transitions) {
if (CGT.ProcIndex == ProcModel.Index) {
HasVariants = true;
break;
Expand Down
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