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Simulation memtest oled #1

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Simulation memtest oled #1

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baa6abf
work simulation - 1
kedziorno Dec 7, 2020
6777f5c
add upload scripts
kedziorno Dec 7, 2020
7258d0c
next stage in simulation - ram and flash
kedziorno Dec 7, 2020
f8dcba3
achieve stTestPassed1
kedziorno Dec 7, 2020
66ddc75
use Z
kedziorno Dec 7, 2020
3b372b4
add oled component
kedziorno Dec 7, 2020
3bc4fc7
add signals and wait for led initialize
kedziorno Dec 7, 2020
d5bcf8a
work - first counter
kedziorno Dec 8, 2020
60cc939
oled refactoring
kedziorno Dec 9, 2020
af78fbb
work - add test status on oled
kedziorno Dec 9, 2020
33cc142
work - add memdb line on oled
kedziorno Dec 10, 2020
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8 changes: 6 additions & 2 deletions DemoWithMemCfg.ucf
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Original file line number Diff line number Diff line change
@@ -1,3 +1,7 @@
# i2c
NET "SDA" LOC = "L15";
NET "SCK" LOC = "K12";

# clock pin for Nexys 2 Board
NET "clk" LOC= "B8"; # Bank = 0 , Pin name = IP_L13P_0/GCLK8 , Type = GCLK , Sch name = GCLK0
NET "clk" CLOCK_DEDICATED_ROUTE = FALSE;
Expand Down Expand Up @@ -199,8 +203,8 @@
NET "PIO<37>" LOC= "B14" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L04P_0 , Type = I/O , Sch name = R-IO38
NET "PIO<38>" LOC= "A16" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L01N_0 , Type = I/O , Sch name = R-IO39
NET "PIO<39>" LOC= "B16" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L01P_0 , Type = I/O , Sch name = R-IO40
NET "PIO<40>" LOC= "L15" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L09N_1/A11 , Type = DUAL , Sch name = JA1
NET "PIO<41>" LOC= "K12" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L11N_1/A9/RHCLK1 , Type = RHCLK/DUAL , Sch name = JA2
#NET "PIO<40>" LOC= "L15" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L09N_1/A11 , Type = DUAL , Sch name = JA1
#NET "PIO<41>" LOC= "K12" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L11N_1/A9/RHCLK1 , Type = RHCLK/DUAL , Sch name = JA2
NET "PIO<42>" LOC= "L17" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L10N_1/VREF_1 , Type = VREF , Sch name = JA3
NET "PIO<43>" LOC= "M15" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L07P_1 , Type = I/O , Sch name = JA4
NET "PIO<44>" LOC= "K13" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L11P_1/A10/RHCLK0 , Type = RHCLK/DUAL , Sch name = JA7
Expand Down
647 changes: 352 additions & 295 deletions DemoWithMemCfg.vhf
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86 changes: 53 additions & 33 deletions DemoWithMemTestMemCfgSyncVgaPs2.xise
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21 changes: 7 additions & 14 deletions EppCtrl.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -201,17 +201,10 @@ architecture Behavioral of EppCtrl is
-- state machine.
-- The states are such a way assigned that each transition
-- changes a single state register bit (Grey code - like)
constant stEppReady : std_logic_vector(2 downto 0) := "000";
constant stEppStb : std_logic_vector(2 downto 0) := "010";
constant stEppRegTransf : std_logic_vector(2 downto 0) := "110";
constant stEppSetProc : std_logic_vector(2 downto 0) := "011";
constant stEppLaunchProc: std_logic_vector(2 downto 0) := "111";
constant stEppWaitProc : std_logic_vector(2 downto 0) := "101";
constant stEppDone : std_logic_vector(2 downto 0) := "100";
type eppstate is (stEppReady,stEppStb,stEppRegTransf,stEppSetProc,stEppLaunchProc,stEppWaitProc,stEppDone);

-- Epp state register and next state signal for the Epp FSM
signal stEppCur: std_logic_vector(2 downto 0) := stEppReady;
signal stEppNext: std_logic_vector(2 downto 0);
signal stEppCur,stEppNext : eppstate;

-- The attribute lines below prevent the ISE compiler to extract and
-- optimize the state machines.
Expand Down Expand Up @@ -258,7 +251,7 @@ begin
-- Synchronized Epp inputs:
process(clk)
begin
if clk'event and clk='1' then
if (rising_edge(clk)) then
if stEppCur = stEppReady then
ctlEppRdCycleOut <= '0';
elsif stEppCur = stEppStb then
Expand Down Expand Up @@ -287,15 +280,15 @@ begin
and EppDstb = '0'
and EppWr = '0' else
'0';
ctlEppStartOut <= '1' when stEppCur = stEppLaunchProc else
ctlEppStartOut <= '1' when stEppCur = stEppLaunchProc else
'0';

------------------------------------------------------------------------
-- EPP Interface Control State Machine
------------------------------------------------------------------------
process (clk)
begin
if clk = '1' and clk'Event then
if(rising_edge(clk)) then
if EppRst = '0' then
stEppCur <= stEppReady;
else
Expand All @@ -304,7 +297,7 @@ begin
end if;
end process;

process (stEppCur)
process (clk,stEppCur)
begin
case stEppCur is
-- Idle state waiting for the beginning of an EPP cycle
Expand Down Expand Up @@ -367,7 +360,7 @@ begin

process (clk, ctlEppAwr)
begin
if clk = '1' and clk'Event then
if (rising_edge(clk)) then
if ctlEppAwr = '1' then
regEppAdrOut <= EppDBIn;
end if;
Expand Down
40 changes: 21 additions & 19 deletions NexysOnBoardMemCtrl.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -187,6 +187,7 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;

entity NexysOnBoardMemCtrl is
Port(
Expand Down Expand Up @@ -264,6 +265,7 @@ architecture Behavioral of NexysOnBoardMemCtrl is
constant stMsmDWr02: std_logic_vector(3 downto 0) := "0110";
constant stMsmDir03: std_logic_vector(3 downto 0) := "1110";
constant stMsmDRd02: std_logic_vector(3 downto 0) := "1010";
--type state is (stMsmReady,stMsmFwr01,stMsmFwr02,stMsmFwr03,stMsmFwr04,stMsmFwr05,stMsmFwr06,stMsmFwr07,stMsmAdInc,stMsmDone,stMsmBlind,stMsmDir01,stMsmDWr02,stMsmDir03,stMsmDRd02);

-- Epp Data register addresses
constant MemCtrlReg: std_logic_vector(2 downto 0) := "000";
Expand Down Expand Up @@ -539,7 +541,7 @@ ctlMsmRamCs <= '0'
-- Memory Control Register
process (clk, ctlMsmDwrIn)
begin
if clk = '1' and clk'Event then
if (rising_edge(clk)) then
if ctlMsmDwrIn = '1' and -- write cycle
regEppAdrIn(2 downto 0) = MemCtrlReg and -- MemCtrlReg addressed
ComponentSelect = '1' then -- NexysOnBoardMemCtrl comp. selected
Expand All @@ -551,7 +553,7 @@ ctlMsmRamCs <= '0'
-- Memory Address Register/Counter
MsmAdrL: process (clk, ctlMsmDwrIn, ctlMsmAdrInc)
begin
if clk = '1' and clk'Event then
if (rising_edge(clk)) then
if ctlMsmAdrInc = '1' then -- automatic memory cycle
regMemAdr(7 downto 0) <= regMemAdr(7 downto 0) + 1; -- inc. address
elsif ctlMsmDwrIn = '1' and -- Epp write cycle
Expand All @@ -566,7 +568,7 @@ MsmAdrL: process (clk, ctlMsmDwrIn, ctlMsmAdrInc)

MsmAdrM: process (clk, ctlMsmDwrIn, ctlMsmAdrInc)
begin
if clk = '1' and clk'Event then
if (rising_edge(clk)) then
if ctlMsmAdrInc = '1' and -- automatic memory cycle
carryoutL = '1' then -- lower byte rollover
regMemAdr(15 downto 8) <= regMemAdr(15 downto 8) + 1;--inc. address
Expand All @@ -582,7 +584,7 @@ MsmAdrM: process (clk, ctlMsmDwrIn, ctlMsmAdrInc)

MsmAdrH: process (clk, ctlMsmDwrIn, ctlMsmAdrInc)
begin
if clk = '1' and clk'Event then
if (rising_edge(clk)) then
if ctlMsmAdrInc = '1' and -- automatic memory cycle
carryoutL = '1' and -- lower byte rollover
carryoutM = '1' then -- middle byte rollover
Expand All @@ -598,7 +600,7 @@ MsmAdrH: process (clk, ctlMsmDwrIn, ctlMsmAdrInc)
-- Memory write data holding register
process (clk, ctlMsmDwrIn)
begin
if clk = '1' and clk'Event then
if (rising_edge(clk)) then
if ctlMsmDwrIn = '1' and -- Epp write cycle
(regEppAdrIn(2 downto 0) = RamAutoRW or -- | Any register holding
regEppAdrIn(2 downto 0) = FlashAutoRW or-- | data to be written
Expand All @@ -616,15 +618,15 @@ MsmAdrH: process (clk, ctlMsmDwrIn, ctlMsmAdrInc)
-- Memory read register: - holds data after an automatic read
process (clk)
begin
if clk = '1' and clk'Event then
if (rising_edge(clk)) then
if stMsmCur = stMsmDRd02 then -- direct read state
if ctlMcrWord = '1' and -- word mode
regMemAdr(0) = '1' then -- odd address
null; -- should never happen
elsif ctlMcrWord = '1' and -- word mode
regMemAdr(0) = '0' then -- even address
regMemRdData <= busMemIn(7 downto 0); --update regMemRdData
regMemRdDataAux <= busMemIn(15 downto 8);
regMemRdDataAux <= busMemIn(15 downto 8);
-- update auxiliary regMemRdData
elsif ctlMcrWord = '0' and -- byte mode
regMemAdr(0) = '0' then -- even address
Expand Down Expand Up @@ -653,12 +655,12 @@ MsmAdrH: process (clk, ctlMsmDwrIn, ctlMsmAdrInc)

process (clk)
begin
if clk = '1' and clk'Event then
if (rising_edge(clk)) then
stMsmCur <= stMsmNext;
end if;
end process;

process (stMsmCur)
process (clk,stMsmCur)

variable flagMsmCycle: std_logic; -- 1 => Msm cycle requested
variable flagBlindCycle: std_logic; -- 1 => Blind Msm cycle requested:
Expand Down Expand Up @@ -713,35 +715,35 @@ MsmAdrH: process (clk, ctlMsmDwrIn, ctlMsmAdrInc)

-- Automatic flash write cont.
when stMsmFwr01 =>
if DelayCnt = "00101" then
if std_match(DelayCnt(4 downto 0),"00101") then
stMsmNext <= stMsmFwr02;
else
stMsmNext <= stMsmFwr01;
end if;

when stMsmFwr02 =>
if DelayCnt = "00111" then
if std_match(DelayCnt(4 downto 0),"00111") then
stMsmNext <= stMsmFwr03;
else
stMsmNext <= stMsmFwr02;
end if;

when stMsmFwr03 =>
if DelayCnt = "01101" then
if std_match(DelayCnt(4 downto 0),"01101") then
stMsmNext <= stMsmFwr04;
else
stMsmNext <= stMsmFwr03;
end if;

when stMsmFwr04 =>
if DelayCnt = "01101" then
if std_match(DelayCnt(4 downto 0),"01101") then
stMsmNext <= stMsmFwr05;
else
stMsmNext <= stMsmFwr04;
end if;

when stMsmFwr05 =>
if DelayCnt = "--101" then
if std_match(DelayCnt(4 downto 0),"--101") then
if busMemIn(7) = '0' then
stMsmNext <= stMsmFwr06;
else
Expand All @@ -752,14 +754,14 @@ MsmAdrH: process (clk, ctlMsmDwrIn, ctlMsmAdrInc)
end if;

when stMsmFwr06 =>
if DelayCnt = "--111" then
if std_match(DelayCnt(4 downto 0),"--111") then
stMsmNext <= stMsmFwr07;
else
stMsmNext <= stMsmFwr06;
end if;

when stMsmFwr07 =>
if DelayCnt = "--101" then
if std_match(DelayCnt(4 downto 0),"--101") then
if busMemIn(7) = '1' then
stMsmNext <= stMsmAdInc;
else
Expand All @@ -783,15 +785,15 @@ MsmAdrH: process (clk, ctlMsmDwrIn, ctlMsmAdrInc)

-- Direct write
when stMsmDWr02 =>
if DelayCnt = "--000" then
if std_match(DelayCnt(4 downto 0),"--000") then
stMsmNext <= stMsmDir03;
else
stMsmNext <= stMsmDWr02; -- keep state
end if;

-- Direct read cont.
when stMsmDRd02 =>
if DelayCnt = "--000" then
if std_match(DelayCnt(4 downto 0),"--000") then
stMsmNext <= stMsmDir03;
else
stMsmNext <= stMsmDRd02; -- keep state
Expand Down Expand Up @@ -830,7 +832,7 @@ MsmAdrH: process (clk, ctlMsmDwrIn, ctlMsmAdrInc)

process (clk)
begin
if clk'event and clk = '1' then
if (rising_edge(clk)) then
if stMsmCur = stMsmReady then
DelayCnt <= "00000";
else
Expand Down
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