GitHub - hnorth99/ArmPipelinedCpu: 64 bit Pipelined Cpu for Arm Instruction Set

hnorth99 / ArmPipelinedCpu Public

64 bit Pipelined Cpu for Arm Instruction Set

Notifications

Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
test		test
D_FF.sv		D_FF.sv
D_FF_64.sv		D_FF_64.sv
add_sub.sv		add_sub.sv
add_sub_64.sv		add_sub_64.sv
adder64.sv		adder64.sv
alu.sv		alu.sv
alu_queue.sv		alu_queue.sv
alu_queue_sub.sv		alu_queue_sub.sv
bitwise_and_64.sv		bitwise_and_64.sv
bitwise_or_64.sv		bitwise_or_64.sv
bitwise_xor_64.sv		bitwise_xor_64.sv
datamem.sv		datamem.sv
datamem_queue.sv		datamem_queue.sv
datamem_queue_sub.sv		datamem_queue_sub.sv
eD_FF.sv		eD_FF.sv
edecoder2_4.sv		edecoder2_4.sv
edecoder3_8.sv		edecoder3_8.sv
edecoder5_32.sv		edecoder5_32.sv
flag_handler.sv		flag_handler.sv
forwarding_unit.sv		forwarding_unit.sv
full_adder.sv		full_adder.sv
instruction_decoder.sv		instruction_decoder.sv
instruction_handler.sv		instruction_handler.sv
instructmem.sv		instructmem.sv
math.sv		math.sv
mux16_1.sv		mux16_1.sv
mux2_1.sv		mux2_1.sv
mux2_1_32x.sv		mux2_1_32x.sv
mux2_1_5x.sv		mux2_1_5x.sv
mux2_1_64x.sv		mux2_1_64x.sv
mux32_1.sv		mux32_1.sv
mux32_1_64x.sv		mux32_1_64x.sv
mux4_1.sv		mux4_1.sv
mux4_1_32x.sv		mux4_1_32x.sv
mux4_1_64x.sv		mux4_1_64x.sv
mux8_1.sv		mux8_1.sv
mux8_1_64x.sv		mux8_1_64x.sv
nor_64.sv		nor_64.sv
processor.sv		processor.sv
regfile.sv		regfile.sv
regfileread_queue.sv		regfileread_queue.sv
regfilewrite_queue.sv		regfilewrite_queue.sv
regfilewrite_queue_sub.sv		regfilewrite_queue_sub.sv
register5.sv		register5.sv
register5_3x.sv		register5_3x.sv
register64.sv		register64.sv
register64_32x.sv		register64_32x.sv
register64_3x.sv		register64_3x.sv
shift_left_2.sv		shift_left_2.sv
sign_extender.sv		sign_extender.sv
swap.sv		swap.sv
zero_extender.sv		zero_extender.sv