feat: AMD support larger extended function entries

[JackThomson2]

Changes

Updated the logic for setting the largest extended function entry, to take the largest between host CPU value and 0x8000_0021. The minimum has also been bumped to 0x8000_0021 to allow setting values regarding SRSO.

Reason

Currently we cap the largest entry to 0x8000001d which prevents extra entries being passed, of interest is 0x8000_0021 which is used to inform the guest that the appropriate SRSO microcode updates have been applied

License Acceptance

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CONTRIBUTING.md.

PR Checklist

• I have read and understand CONTRIBUTING.md.
• I have run tools/devtool checkstyle to verify that the PR passes the
  automated style checks.
• I have described what is done in these changes, why they are needed, and
  how they are solving the problem in a clear and encompassing way.
• I have updated any relevant documentation (both in code and in the docs)
  in the PR.
• I have mentioned all user-facing changes in CHANGELOG.md.
• If a specific issue led to this PR, this PR closes the issue.
• When making API changes, I have followed the
  Runbook for Firecracker API changes.
• I have tested all new and changed functionalities in unit tests and/or
  integration tests.
• I have linked an issue to every new TODO.

---

• This functionality cannot be added in rust-vmm.

[codecov]

Codecov Report

All modified and coverable lines are covered by tests ✅

Project coverage is 83.95%. Comparing base (94826a8) to head (38300e6).

Additional details and impacted files

@@           Coverage Diff           @@
##             main    #4995   +/-   ##
=======================================
  Coverage   83.95%   83.95%           
=======================================
  Files         248      248           
  Lines       27839    27845    +6     
=======================================
+ Hits        23371    23377    +6     
  Misses       4468     4468           

Flag	Coverage Δ
5.10-c5n.metal	84.53% <ø> (ø)
5.10-m5n.metal	84.51% <ø> (-0.01%)	⬇️
5.10-m6a.metal	83.80% <100.00%> (-0.01%)	⬇️
5.10-m6g.metal	80.63% <ø> (ø)
5.10-m6i.metal	84.50% <ø> (-0.01%)	⬇️
5.10-m7g.metal	80.63% <ø> (ø)
6.1-c5n.metal	84.52% <ø> (ø)
6.1-m5n.metal	84.51% <ø> (-0.01%)	⬇️
6.1-m6a.metal	83.80% <100.00%> (-0.01%)	⬇️
6.1-m6g.metal	80.63% <ø> (-0.01%)	⬇️
6.1-m6i.metal	84.50% <ø> (+<0.01%)	⬆️
6.1-m7g.metal	80.63% <ø> (ø)

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