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Modify macro name and precondition of regfile assertions #11

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merged 2 commits into from
Oct 28, 2024
Merged

Modify macro name and precondition of regfile assertions #11

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57838e0
Rename Regfile macro name
jhsy1209021 Oct 28, 2024
de22c1a
Remove stall from precondition
jhsy1209021 Oct 28, 2024
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2 changes: 1 addition & 1 deletion isa.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -37,7 +37,7 @@ proc setCheckFlag {flagName flagValue} {

# set check flag
setCheckFlag "CheckInstValidAssume" 0
setCheckFlag "RegFileStable" 0
setCheckFlag "RegFile" 0
setCheckFlag "PipeFollower" 0
setCheckFlag "PC_INC4_NO_BRANCH" 0
setCheckFlag "ISA_GROUP_A" 1
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4 changes: 2 additions & 2 deletions property/fv_regfile.sv
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Expand Up @@ -75,13 +75,13 @@ module fv_regfile
//////////////////// Assertion ////////////////////
property write_correct(logic [31:0] duv_rf, rsd_t rf_dst, logic [4:0] rf_index);
@(posedge clk) disable iff (rst)
~(pd_stall_i | id_stall_i) && (rf_dst == rf_index) && rf_we_i
(rf_dst == rf_index) && rf_we_i
|=> ($past(rf_dst_d_i) == duv_rf);
endproperty

property reg_stable(logic [31:0] duv_rf, rsd_t rf_dst, logic [4:0] rf_index);
@(posedge clk) disable iff (rst)
~(pd_stall_i | id_stall_i) && (rf_dst != rf_index) && rf_we_i
(rf_dst != rf_index) && rf_we_i
|=> $stable(duv_rf);
endproperty

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4 changes: 2 additions & 2 deletions property/isa.sv
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Expand Up @@ -743,7 +743,7 @@ module isa (
assert property (CHECK_INST_VALID_ASSUME);
`endif // CheckInstValidAssume

`ifdef RegFileStable
`ifdef RegFile
// Import necessary package
import riscv_opcodes_pkg::rsd_t;

Expand Down Expand Up @@ -786,7 +786,7 @@ module isa (
.pd_stall_i(pd_stall_i),
.id_stall_i(id_stall_i)
);
`endif // RegFileStable
`endif // RegFile

`ifdef PipeFollower
IfToPd :
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