Add cve2 xif

core-v-mini-mcu.core

@@ -39,6 +39,7 @@ filesets:
     files:
     - hw/core-v-mini-mcu/core_v_mini_mcu.sv
     - hw/core-v-mini-mcu/cpu_subsystem.sv
+    - hw/core-v-mini-mcu/cve2_xif_wrapper.sv
     - hw/core-v-mini-mcu/memory_subsystem.sv
     - hw/core-v-mini-mcu/xbar_varlat_one_to_n.sv
     - hw/core-v-mini-mcu/xbar_varlat_n_to_one.sv
@@ -189,13 +190,19 @@ parameters:
     datatype: int
     paramtype: vlogparam
     description: |
-      Enables COREV_PULP custom RISC-V extension on the CV32E40P core. Admitted values: 1|0.
+      Enables COREV_PULP custom RISC-V extensions. Admitted values: 1|0.
     default: 0
   FPU:
     datatype: int
     paramtype: vlogparam
     description: |
-      Enables RV32F RISC-V extension on the CV32E40P core. Admitted values: 1|0.
+      Enables RV32F RISC-V extensions. Admitted values: 1|0.
+    default: 0
+  ZFINX:
+    datatype: int
+    paramtype: vlogparam
+    description: |
+      Enables RV32Zfinx RISC-V extensions. Admitted values: 1|0.
     default: 0
   JTAG_DPI:
     datatype: int
@@ -322,6 +329,7 @@ targets:
     parameters:
     - COREV_PULP
     - FPU
+    - ZFINX
     - JTAG_DPI
     - X_EXT
     - USE_EXTERNAL_DEVICE_EXAMPLE
@@ -391,6 +399,7 @@ targets:
     parameters:
     - COREV_PULP
     - FPU
+    - ZFINX
     - JTAG_DPI
     - X_EXT
     - USE_EXTERNAL_DEVICE_EXAMPLE
@@ -423,6 +432,7 @@ targets:
     parameters:
     - COREV_PULP
     - FPU
+    - ZFINX
     - X_EXT
     - SYNTHESIS=true
     - REMOVE_OBI_FIFO
@@ -445,6 +455,7 @@ targets:
     parameters:
     - COREV_PULP
     - FPU
+    - ZFINX
     - X_EXT
     - SYNTHESIS=true
     - REMOVE_OBI_FIFO
@@ -466,6 +477,7 @@ targets:
     parameters:
     - COREV_PULP
     - FPU
+    - ZFINX
     - X_EXT
     - SYNTHESIS=true
     - REMOVE_OBI_FIFO
@@ -487,6 +499,7 @@ targets:
     - COREV_PULP
     - X_EXT
     - FPU
+    - ZFINX
     - SYNTHESIS=true
     - REMOVE_OBI_FIFO
     filesets_append:
@@ -508,6 +521,7 @@ targets:
     parameters:
       - COREV_PULP
       - FPU
+      - ZFINX
       - X_EXT
       - SYNTHESIS=true
       - VERILATOR=true

docs/source/Extending/index.md

@@ -20,6 +20,17 @@ cd ./build/openhwgroup.org_systems_core-v-mini-mcu_0/sim-verilator
 
 The program should terminate with value 0.
 
+Also, you can try the FPU-like coprocessor with a CV-X-IF extended cve2 using the Zfinx extensions (i.e. the Floating-Point register-file is actually the same as the General-Purpose register-file).
+First, you need the OpenHW Group CORE-V Compiler, then:
+
+```
+make mcu-gen
+make verilator-sim FUSESOC_PARAM="--X_EXT=1 --ZFINX=1"
+make app PROJECT=example_matfadd COMPILER_PREFIX=riscv32-corev- ARCH=rv32imc_zicsr_zifencei_zfinx
+cd ./build/openhwgroup.org_systems_core-v-mini-mcu_0/sim-verilator
+./Vtestharness +firmware=../../../sw/build/main.hex
+```
+
 To learn how to extend X-HEEP you can read the guides in this section.
 
 ```{toctree}

hw/core-v-mini-mcu/cpu_subsystem.sv

@@ -59,24 +59,24 @@ module cpu_subsystem
 
   if (CPU_TYPE == cv32e20) begin : gen_cv32e20
 
-    cve2_top #(
-        .MHPMCounterNum('0)
+    cve2_xif_wrapper #(
+        .XInterface(X_EXT)
     ) cv32e20_i (
         .clk_i (clk_i),
         .rst_ni(rst_ni),
 
         .test_en_i(1'b0),
-        .ram_cfg_i('0),
 
-        .hart_id_i  (32'h0),
+        .hart_id_i(32'h0),
         .boot_addr_i(BOOT_ADDR),
+        .dm_exception_addr_i(32'h0),
+        .dm_halt_addr_i(DM_HALTADDRESS),
 
         .instr_addr_o  (core_instr_req_o.addr),
         .instr_req_o   (core_instr_req_o.req),
         .instr_rdata_i (core_instr_resp_i.rdata),
         .instr_gnt_i   (core_instr_resp_i.gnt),
         .instr_rvalid_i(core_instr_resp_i.rvalid),
-        .instr_err_i   (1'b0),
 
         .data_addr_o  (core_data_req_o.addr),
         .data_wdata_o (core_data_req_o.wdata),
@@ -86,18 +86,46 @@ module cpu_subsystem
         .data_rdata_i (core_data_resp_i.rdata),
         .data_gnt_i   (core_data_resp_i.gnt),
         .data_rvalid_i(core_data_resp_i.rvalid),
-        .data_err_i   (1'b0),
 
         .irq_software_i(irq_i[3]),
         .irq_timer_i   (irq_i[7]),
         .irq_external_i(irq_i[11]),
         .irq_fast_i    (irq_i[31:16]),
-        .irq_nm_i      (1'b0),
 
         .debug_req_i(debug_req_i),
-        .dm_exception_addr_i(32'h0),
-        .dm_halt_addr_i(DM_HALTADDRESS),
-        .crash_dump_o(),
+        .debug_halted_o(),
+
+        // CORE-V-XIF
+        // Compressed interface
+        .x_compressed_valid_o(xif_compressed_if.compressed_valid),
+        .x_compressed_ready_i(xif_compressed_if.compressed_ready),
+        .x_compressed_req_o  (xif_compressed_if.compressed_req),
+        .x_compressed_resp_i (xif_compressed_if.compressed_resp),
+
+        // Issue Interface
+        .x_issue_valid_o(xif_issue_if.issue_valid),
+        .x_issue_ready_i(xif_issue_if.issue_ready),
+        .x_issue_req_o  (xif_issue_if.issue_req),
+        .x_issue_resp_i (xif_issue_if.issue_resp),
+
+        // Commit Interface
+        .x_commit_valid_o(xif_commit_if.commit_valid),
+        .x_commit_o(xif_commit_if.commit),
+
+        // Memory Request/Response Interface
+        .x_mem_valid_i(xif_mem_if.mem_valid),
+        .x_mem_ready_o(xif_mem_if.mem_ready),
+        .x_mem_req_i  (xif_mem_if.mem_req),
+        .x_mem_resp_o (xif_mem_if.mem_resp),
+
+        // Memory Result Interface
+        .x_mem_result_valid_o(xif_mem_result_if.mem_result_valid),
+        .x_mem_result_o(xif_mem_result_if.mem_result),
+
+        // Result Interface
+        .x_result_valid_i(xif_result_if.result_valid),
+        .x_result_ready_o(xif_result_if.result_ready),
+        .x_result_i(xif_result_if.result),
 
         .fetch_enable_i(fetch_enable),
 

hw/core-v-mini-mcu/cpu_subsystem.sv.tpl

@@ -59,30 +59,30 @@ module cpu_subsystem
 
   if (CPU_TYPE == cv32e20) begin : gen_cv32e20
 
-    cve2_top #(
+    cve2_xif_wrapper #(
 % if cve2_rv32e:
         .RV32E(${cve2_rv32e}),
 % endif
 % if cve2_rv32m:
         .RV32M(${cve2_rv32m}),
 % endif
-        .MHPMCounterNum('0)
+        .XInterface(X_EXT)
     ) cv32e20_i (
         .clk_i (clk_i),
         .rst_ni(rst_ni),
 
         .test_en_i(1'b0),
-        .ram_cfg_i('0),
 
         .hart_id_i  (32'h0),
         .boot_addr_i(BOOT_ADDR),
+        .dm_exception_addr_i(32'h0),
+        .dm_halt_addr_i(DM_HALTADDRESS),
 
         .instr_addr_o  (core_instr_req_o.addr),
         .instr_req_o   (core_instr_req_o.req),
         .instr_rdata_i (core_instr_resp_i.rdata),
         .instr_gnt_i   (core_instr_resp_i.gnt),
         .instr_rvalid_i(core_instr_resp_i.rvalid),
-        .instr_err_i   (1'b0),
 
         .data_addr_o  (core_data_req_o.addr),
         .data_wdata_o (core_data_req_o.wdata),
@@ -92,18 +92,46 @@ module cpu_subsystem
         .data_rdata_i (core_data_resp_i.rdata),
         .data_gnt_i   (core_data_resp_i.gnt),
         .data_rvalid_i(core_data_resp_i.rvalid),
-        .data_err_i   (1'b0),
 
         .irq_software_i(irq_i[3]),
         .irq_timer_i   (irq_i[7]),
         .irq_external_i(irq_i[11]),
         .irq_fast_i    (irq_i[31:16]),
-        .irq_nm_i      (1'b0),
 
-        .debug_req_i (debug_req_i),
-        .dm_exception_addr_i(32'h0),
-        .dm_halt_addr_i(DM_HALTADDRESS),
-        .crash_dump_o(),
+        .debug_req_i(debug_req_i),
+        .debug_halted_o(),
+
+        // CORE-V-XIF
+        // Compressed interface
+        .x_compressed_valid_o(xif_compressed_if.compressed_valid),
+        .x_compressed_ready_i(xif_compressed_if.compressed_ready),
+        .x_compressed_req_o  (xif_compressed_if.compressed_req),
+        .x_compressed_resp_i (xif_compressed_if.compressed_resp),
+
+        // Issue Interface
+        .x_issue_valid_o(xif_issue_if.issue_valid),
+        .x_issue_ready_i(xif_issue_if.issue_ready),
+        .x_issue_req_o  (xif_issue_if.issue_req),
+        .x_issue_resp_i (xif_issue_if.issue_resp),
+
+        // Commit Interface
+        .x_commit_valid_o(xif_commit_if.commit_valid),
+        .x_commit_o(xif_commit_if.commit),
+
+        // Memory Request/Response Interface
+        .x_mem_valid_i(xif_mem_if.mem_valid),
+        .x_mem_ready_o(xif_mem_if.mem_ready),
+        .x_mem_req_i  (xif_mem_if.mem_req),
+        .x_mem_resp_o (xif_mem_if.mem_resp),
+
+        // Memory Result Interface
+        .x_mem_result_valid_o(xif_mem_result_if.mem_result_valid),
+        .x_mem_result_o(xif_mem_result_if.mem_result),
+
+        // Result Interface
+        .x_result_valid_i(xif_result_if.result_valid),
+        .x_result_ready_o(xif_result_if.result_ready),
+        .x_result_i(xif_result_if.result),
 
         .fetch_enable_i(fetch_enable),