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run bus_wrap(f323712) on EF_PSRAM_CTRL(43c5d66)
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ef-staff committed Feb 20, 2025
1 parent 43c5d66 commit 223a69b
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40 changes: 16 additions & 24 deletions README.md
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Expand Up @@ -25,24 +25,18 @@ The controller was verified against the Verilog model of Microchip M23LC1024 for
#### Wrapped IP System Integration

```verilog
EF_PSRAM_CTRL_AHBL INST (
.HCLK(CLK),
.HRESETn(RESETn),
.HADDR(HADDR),
.HWRITE(HWRITE),
.HSEL(HSEL),
.HTRANS(HTRANS),
.HWDATA(HWDATA),
.HRDATA(HRDATA),
.HREADY(HREADY),
.HREADYOUT(HREADYOUT),
.sck(sck),
.ce_n(ce_n),
.din(din),
.dout(dout),
.douten(douten)
EF_PSRAM_CTRL_APB INST (
`TB_AHBL_SLAVE_CONN,
.sck(sck)
.ce_n(ce_n)
.din(din)
.dout(dout)
.douten(douten)
);
```
> **_NOTE:_** `TB_APB_SLAVE_CONN is a convenient macro provided by [BusWrap](https://github.com/efabless/BusWrap/tree/main).
### Wrappers with DFT support
Wrappers in the directory ``/hdl/rtl/bus_wrappers/DFT`` have an extra input port ``sc_testmode`` to disable the clock gate whenever the scan chain testmode is enabled.
### External IO interfaces
|IO name|Direction|Width|Description|
|---|---|---|---|
Expand All @@ -51,6 +45,8 @@ EF_PSRAM_CTRL_AHBL INST (
|din|input|4|SPI Master data in , slave out|
|dout|output|4|SPI Master data out , slave in|
|douten|output|4|SPI Master data out enable|
### Interrupt Request Line (irq)
This IP generates interrupts on specific events, which are described in the [Interrupt Flags](#interrupt-flags) section bellow. The IRQ port should be connected to the system interrupt controller.

## Implementation example

Expand All @@ -61,11 +57,7 @@ The following table is the result for implementing the EF_PSRAM_CTRL IP with dif
|EF_PSRAM_CTRL_AHBL|TBD|TBD|
## The Programmer's Interface

### Memory Map
|Region|Description|
|------|-----------|
|```0x07FF_FFFF - 0x0000_0000```| Data Access |
|```0x0FFF_FFFF - 0x0800_0000```| Configuration Registers|

### Registers

|Name|Offset|Reset Value|Access Mode|Description|
Expand Down Expand Up @@ -120,8 +112,8 @@ Initiate Exit QPI (XQPI) Mode process Register
<img src="https://svg.wavedrom.com/{reg:[{name:'exit_qpi', bits:1},{bits: 31}], config: {lanes: 2, hflip: true}} "/>

## Firmware Drivers:
Firmware drivers for EF_PSRAM_CTRL can be found in the [Drivers](https://github.com/efabless/EFIS/tree/main/Drivers) directory in the [EFIS](https://github.com/efabless/EFIS) (Efabless Firmware Interface Standard) repo. EF_PSRAM_CTRL driver documentation is available [here](https://github.com/efabless/EFIS/blob/main/Drivers/docs/EF_Driver_PSRAM_CTRL/README.md).
You can also find an example C application using the EF_PSRAM_CTRL drivers [here](https://github.com/efabless/EFIS/tree/main/Drivers/docs/EF_Driver_PSRAM_CTRL/example).
Firmware drivers for EF_PSRAM_CTRL can be found in the [Drivers](https://github.com/efabless/EFIS/tree/main/Drivers) directory in the [EFIS](https://github.com/efabless/EFIS) (Efabless Firmware Interface Standard) repo. EF_PSRAM_CTRL driver documentation is available [here](https://github.com/efabless/EFIS/blob/main/Drivers/Docs/EF_PSRAM_CTRL/README.md).
You can also find an example C application using the EF_PSRAM_CTRL drivers [here](https://github.com/efabless/EFIS/tree/main/Drivers/Docs/EF_PSRAM_CTRL/example).
## Installation:
You can install the IP either by cloning this repository or by using [IPM](https://github.com/efabless/IPM).
### 1. Using [IPM](https://github.com/efabless/IPM):
Expand All @@ -148,4 +140,4 @@ You can install the IP either by cloning this repository or by using [IPM](https
|ce_n|output|1|SPI Master slave select.|
|din|input|4|SPI Master data in , slave out|
|dout|output|4|SPI Master data out , slave in|
|douten|output|4|SPI Master data out enable|
|douten|output|4|SPI Master data out enable|
121 changes: 121 additions & 0 deletions fw/EF_PSRAM_CTRL_regs.h
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@@ -0,0 +1,121 @@
/*
Copyright 2024 Efabless Corp.
Author: Efabless Corp. ([email protected])
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/

#ifndef EF_PSRAM_CTRLREGS_H
#define EF_PSRAM_CTRLREGS_H


/******************************************************************************
* Includes
******************************************************************************/
#include <stdint.h>

/******************************************************************************
* Macros and Constants
******************************************************************************/

#ifndef IO_TYPES
#define IO_TYPES
#define __R volatile const uint32_t
#define __W volatile uint32_t
#define __RW volatile uint32_t
#endif

#define EF_PSRAM_CTRL_RD_CMD_REG_RD_CMD_BIT ((uint32_t)0)
#define EF_PSRAM_CTRL_RD_CMD_REG_RD_CMD_MASK ((uint32_t)0xff)
#define EF_PSRAM_CTRL_RD_CMD_REG_MAX_VALUE ((uint32_t)0xFF)

#define EF_PSRAM_CTRL_WR_CMD_REG_WR_CMD_BIT ((uint32_t)0)
#define EF_PSRAM_CTRL_WR_CMD_REG_WR_CMD_MASK ((uint32_t)0xff)
#define EF_PSRAM_CTRL_WR_CMD_REG_MAX_VALUE ((uint32_t)0xFF)

#define EF_PSRAM_CTRL_EQPI_CMD_REG_EQPI_CMD_BIT ((uint32_t)0)
#define EF_PSRAM_CTRL_EQPI_CMD_REG_EQPI_CMD_MASK ((uint32_t)0xff)
#define EF_PSRAM_CTRL_EQPI_CMD_REG_MAX_VALUE ((uint32_t)0xFF)

#define EF_PSRAM_CTRL_XQPI_CMD_REG_XQPI_CMD_BIT ((uint32_t)0)
#define EF_PSRAM_CTRL_XQPI_CMD_REG_XQPI_CMD_MASK ((uint32_t)0xff)
#define EF_PSRAM_CTRL_XQPI_CMD_REG_MAX_VALUE ((uint32_t)0xFF)

#define EF_PSRAM_CTRL_WAIT_STATES_REG_WAIT_STATES_BIT ((uint32_t)0)
#define EF_PSRAM_CTRL_WAIT_STATES_REG_WAIT_STATES_MASK ((uint32_t)0xf)
#define EF_PSRAM_CTRL_WAIT_STATES_REG_MAX_VALUE ((uint32_t)0xF)

#define EF_PSRAM_CTRL_MODE_REG_MODE_BIT ((uint32_t)0)
#define EF_PSRAM_CTRL_MODE_REG_MODE_MASK ((uint32_t)0x3)
#define EF_PSRAM_CTRL_MODE_REG_MAX_VALUE ((uint32_t)0x3)

#define EF_PSRAM_CTRL_ENTER_QPI_REG_ENTER_QPI_BIT ((uint32_t)0)
#define EF_PSRAM_CTRL_ENTER_QPI_REG_ENTER_QPI_MASK ((uint32_t)0x1)
#define EF_PSRAM_CTRL_ENTER_QPI_REG_MAX_VALUE ((uint32_t)0x1)

#define EF_PSRAM_CTRL_EXIT_QPI_REG_EXIT_QPI_BIT ((uint32_t)0)
#define EF_PSRAM_CTRL_EXIT_QPI_REG_EXIT_QPI_MASK ((uint32_t)0x1)
#define EF_PSRAM_CTRL_EXIT_QPI_REG_MAX_VALUE ((uint32_t)0x1)





/******************************************************************************
* Typedefs and Enums
******************************************************************************/

typedef struct _EF_PSRAM_CTRL_TYPE_ {
__R reserved_0[2097216];
__W rd_cmd;
__R reserved_1[63];
__W wr_cmd;
__R reserved_2[127];
__W eqpi_cmd;
__R reserved_3[255];
__W xqpi_cmd;
__R reserved_4[511];
__W wait_states;
__R reserved_5[1023];
__W mode;
__R reserved_6[2047];
__W enter_qpi;
__R reserved_7[4095];
__W exit_qpi;
} EF_PSRAM_CTRL_TYPE;

typedef struct _EF_PSRAM_CTRL_TYPE_ *EF_PSRAM_CTRL_TYPE_PTR; // Pointer to the register structure


/******************************************************************************
* Function Prototypes
******************************************************************************/



/******************************************************************************
* External Variables
******************************************************************************/




#endif

/******************************************************************************
* End of File
******************************************************************************/


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