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Allow BoringUtils.bore to work on probes (#3908) (#3910)
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Extends BorginUtils.bore (and related) to work where the source is a
probe.  Currently, if a user tries to do this, they will get an error
about being unable to probe a probe because the old code would
unconditionally wrap whatever the source was in `Probe`/`RWProbe`.  Change
this to not wrap if the source is already a probe.

Signed-off-by: Schuyler Eldridge <[email protected]>
(cherry picked from commit 67f51b8)

Co-authored-by: Schuyler Eldridge <[email protected]>
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mergify[bot] and seldridge authored Mar 6, 2024
1 parent 9769d54 commit db6a64a
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Showing 2 changed files with 25 additions and 3 deletions.
11 changes: 8 additions & 3 deletions src/main/scala/chisel3/util/experimental/BoringUtils.scala
Original file line number Diff line number Diff line change
Expand Up @@ -224,9 +224,14 @@ object BoringUtils {
else if (DataMirror.hasOuterFlip(source)) Flipped(chiselTypeOf(source))
else chiselTypeOf(source)
def purePortType = createProbe match {
case Some(pi) if pi.writable => RWProbe(purePortTypeBase)
case Some(pi) => Probe(purePortTypeBase)
case None => purePortTypeBase
case Some(pi) =>
// If the source is already a probe, don't double wrap it in a probe.
purePortTypeBase.probeInfo match {
case Some(_) => purePortTypeBase
case None if pi.writable => RWProbe(purePortTypeBase)
case None => Probe(purePortTypeBase)
}
case None => purePortTypeBase
}
def isPort(d: Data): Boolean = d.topBindingOpt match {
case Some(PortBinding(_)) => true
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17 changes: 17 additions & 0 deletions src/test/scala/chiselTests/BoringUtilsTapSpec.scala
Original file line number Diff line number Diff line change
Expand Up @@ -495,4 +495,21 @@ class BoringUtilsTapSpec extends ChiselFlatSpec with ChiselRunners with Utils wi
val verilog = circt.stage.ChiselStage.emitSystemVerilog(new Foo)
}

it should "allow tapping a probe" in {
class Bar extends RawModule {
val a = IO(probe.Probe(Bool()))
}
class Foo extends RawModule {
val b = IO(probe.Probe(Bool()))
val bar = Module(new Bar)
probe.define(b, BoringUtils.tap(bar.a))
}

val chirrtl = circt.stage.ChiselStage.emitCHIRRTL(new Foo)

matchesAndOmits(chirrtl)(
"define b = bar.a"
)()
}

}

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