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Making CORE-V safe for the world to use.
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Making CORE-V safe for the world to use.

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  1. riscv-dv Public

    Forked from chipsalliance/riscv-dv

    SV/UVM based instruction generator for RISC-V processor verification

    SystemVerilog 1 1

  2. openhwgroup/cv32e40p Public

    CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

    SystemVerilog 1k 436

  3. openhwgroup/core-v-verif Public

    Functional verification project for the CORE-V family of RISC-V cores.

    Assembly 493 232

  4. openhwgroup/programs Public

    Documentation for the OpenHW Group's set of CORE-V RISC-V cores

    HTML 206 97

245 contributions in the last year

Contribution Graph
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Activity overview

Contributed to openhwgroup/core-v-verif, openhwgroup/programs, openhwgroup/core-v-cores and 25 other repositories
Loading A graph representing MikeOpenHWGroup's contributions from February 25, 2024 to February 26, 2025. The contributions are 43% code review, 35% commits, 11% pull requests, 11% issues.

Contribution activity

February 2025

Created 3 repositories

Created a pull request in openhwgroup/cv32e40p that received 2 comments

Update Ubuntu runner version

Update in reaction to message from GitHub: The Ubuntu 20.04 runner image will be fully unsupported by April 1, 2025.

+2 −2 lines changed 2 comments
Opened 5 other pull requests in 4 repositories
Reviewed 4 pull requests in 3 repositories

Created an issue in openhwgroup/openhwgroup.org that received 5 comments

"RISC-v" should be "RISC-V"

On the homepage of https://www.openhwfoundation.org/ is says "Open Source RISC-v CPU". The "v" should be upper-case.

5 comments
Opened 3 other issues in 2 repositories
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