RISC-V_64-bit_ALU

A basic ALU and ALU Control Unit Implementation using Verilog

Members:

testbenches.v :- This file contains testbench modules of all the core modules, 1-bit ALUs, including a testbench module to test the outputs for different functions of the ALU
Utility_Modules.v :- This file contains basic modules used in other modules:
1. mux2to1 :- A 2:1 mux
2. mux4to1 :- A 4:1 mux which uses mux2to1
3. fullAdder :- A standard full adder
ALU_1bit.v :- This file contains the ordinary and MSB versions of the 1-bit ALUs. It contains the following modules:
1. ALU_1bit_Ordinary :- It is the orinary version of the 1-bit ALU
2. ALU_1bit_MSB :- It is the MSB version of the 1-bit ALU. It is used at the end of the ALU cascading.
ALU_CU.v :- Contains the module of the ALU Control Unit
ALU_64bit.v :- Contains the cascaded ALUs in a single module

Name		Name	Last commit message	Last commit date
Latest commit History 29 Commits
work		work
ALU_1bit.v		ALU_1bit.v
ALU_1bit.v.bak		ALU_1bit.v.bak
ALU_64bit.v		ALU_64bit.v
ALU_64bit.v.bak		ALU_64bit.v.bak
ALU_CU.v		ALU_CU.v
ALU_CU.v.bak		ALU_CU.v.bak
Control_Unit.v		Control_Unit.v
Data_Memory.v		Data_Memory.v
Data_Memory.v.bak		Data_Memory.v.bak
Execution.v		Execution.v
Execution.v.bak		Execution.v.bak
ID_and_RF.v		ID_and_RF.v
Instruction_Fetch.v		Instruction_Fetch.v
Instruction_Fetch.v.bak		Instruction_Fetch.v.bak
Instruction_Memory.v		Instruction_Memory.v
Memory.v		Memory.v
Pipeline.v		Pipeline.v
README.md		README.md
Register_File.v		Register_File.v
Register_File.v.bak		Register_File.v.bak
Sign_Extension.v		Sign_Extension.v
Sign_Extension.v.bak		Sign_Extension.v.bak
Stage_Testbenches.v		Stage_Testbenches.v
Stage_Testbenches.v.bak		Stage_Testbenches.v.bak
Testing.cr.mti		Testing.cr.mti
Testing.mpf		Testing.mpf
Utility_Modules.v		Utility_Modules.v
Utility_Modules.v.bak		Utility_Modules.v.bak
Write_Back.v		Write_Back.v
branch_select.mem		branch_select.mem
data.mem		data.mem
instructions.mem		instructions.mem
testbenches.v		testbenches.v
testbenches.v.bak		testbenches.v.bak
transcript		transcript
vsim.wlf		vsim.wlf
wave.do		wave.do