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itx_avx512.asm
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itx_avx512.asm
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; Copyright © 2020-2023, VideoLAN and dav1d authors
; Copyright © 2020-2023, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice, this
; list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
%include "config.asm"
%include "ext/x86/x86inc.asm"
%if ARCH_X86_64
SECTION_RODATA 64
const \
dup16_perm, db 0, 1, 0, 1, 2, 3, 2, 3, 4, 5, 4, 5, 6, 7, 6, 7
db 8, 9, 8, 9, 10, 11, 10, 11, 12, 13, 12, 13, 14, 15, 14, 15
db 16, 17, 16, 17, 18, 19, 18, 19, 20, 21, 20, 21, 22, 23, 22, 23
db 24, 25, 24, 25, 26, 27, 26, 27, 28, 29, 28, 29, 30, 31, 30, 31
const \
int8_permA, db 0, 1, 16, 17, 32, 33, 48, 49, 2, 3, 18, 19, 34, 35, 50, 51
db 4, 5, 20, 21, 36, 37, 52, 53, 6, 7, 22, 23, 38, 39, 54, 55
db 8, 9, 24, 25, 40, 41, 56, 57, 10, 11, 26, 27, 42, 43, 58, 59
db 12, 13, 28, 29, 44, 45, 60, 61, 14, 15, 30, 31, 46, 47, 62, 63
int8_permB: db 0, 1, 16, 17, 32, 33, 48, 49, 2, 3, 18, 19, 34, 35, 50, 51
db 8, 9, 24, 25, 40, 41, 56, 57, 10, 11, 26, 27, 42, 43, 58, 59
db 4, 5, 20, 21, 36, 37, 52, 53, 6, 7, 22, 23, 38, 39, 54, 55
db 12, 13, 28, 29, 44, 45, 60, 61, 14, 15, 30, 31, 46, 47, 62, 63
int16_perm: db 0, 1, 32, 33, 2, 3, 34, 35, 4, 5, 36, 37, 6, 7, 38, 39
db 8, 9, 40, 41, 10, 11, 42, 43, 12, 13, 44, 45, 14, 15, 46, 47
db 16, 17, 48, 49, 18, 19, 50, 51, 20, 21, 52, 53, 22, 23, 54, 55
db 24, 25, 56, 57, 26, 27, 58, 59, 28, 29, 60, 61, 30, 31, 62, 63
idtx_16x4p: db 0, 1, 4, 5, 16, 17, 20, 21, 2, 3, 6, 7, 18, 19, 22, 23
db 32, 33, 36, 37, 48, 49, 52, 53, 34, 35, 38, 39, 50, 51, 54, 55
db 8, 9, 12, 13, 24, 25, 28, 29, 10, 11, 14, 15, 26, 27, 30, 31
db 40, 41, 44, 45, 56, 57, 60, 61, 42, 43, 46, 47, 58, 59, 62, 63
idct_8x32p: db 60, 61, 4, 5, 32, 33, 0, 1, 28, 29, 36, 37, 56, 57, 8, 9
db 12, 13, 52, 53, 24, 25, 40, 41, 44, 45, 20, 21, 48, 49, 16, 17
db 62, 63, 2, 3, 6, 7, 58, 59, 54, 55, 10, 11, 14, 15, 50, 51
db 46, 47, 18, 19, 22, 23, 42, 43, 38, 39, 26, 27, 30, 31, 34, 35
idct_16x32p: db 6, 7, 58, 59, 38, 39, 26, 27, 32, 33, 0, 1, 30, 31, 34, 35
db 46, 47, 18, 19, 22, 23, 42, 43, 24, 25, 40, 41, 44, 45, 20, 21
db 62, 63, 2, 3, 48, 49, 16, 17, 56, 57, 8, 9, 14, 15, 50, 51
db 54, 55, 10, 11, 60, 61, 4, 5, 12, 13, 52, 53, 28, 29, 36, 37
end_16x32p: db 0, 32, 1, 48, 2, 36, 3, 52, 16, 40, 17, 56, 18, 44, 19, 60
db 4, 33, 5, 49, 6, 37, 7, 53, 20, 41, 21, 57, 22, 45, 23, 61
db 8, 35, 9, 51, 10, 39, 11, 55, 24, 43, 25, 59, 26, 47, 27, 63
db 12, 34, 13, 50, 14, 38, 15, 54, 28, 42, 29, 58, 30, 46, 31, 62
; packed 4-bit qword shuffle indices
permA: dq 0x1c0d0d1ce0d94040, 0x5849495868fb6262
dq 0x3e2f2f3ef1c85151, 0x7a6b6b7a79ea7373
dq 0x94858594a451c8d9, 0xd0c1c1d02c73eafb
dq 0xb6a7a7b6b540d9c8, 0xf2e3e3f23d62fbea
permB: dq 0x40acbd0fcadb0f40, 0x518e9f3ce8f99604
dq 0xc824352d56128751, 0xd906171e74301e15
dq 0x6271604b03472d62, 0x735342782165b426
dq 0xeaf9e8699f8ea573, 0xfbdbca5abdac3c37
permC: dq 0x9d409d041551c2e0, 0xbf62bf263773a486
dq 0xc88c8c15409dd3f1, 0xeaaeae3762bfb597
dq 0x04d9158c8cc84a68, 0x26fb37aeaeea2c0e
dq 0x5115049dd9045b79, 0x733726bffb263d1f
permD: dq 0x0cda098800041504, 0x0edb09b2028c3726
dq 0x0f11fa9c01150415, 0x0988f326039d2637
dq 0x05640f1108269d8c, 0x05290edb0aaebfae
dq 0x0005000509378c9d, 0xffffffff0bbfaebf
pd_0to15: dd 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
gather8a: dd 0, 2, 1, 3, 8, 10, 9, 11
gather8b: dd 0, 1, 4, 5, 8, 9, 12, 13
gather8c: dd 0, 4, 2, 6, 12, 8, 14, 10
gather8d: dd 0, 19, 1, 18, 2, 17, 3, 16
int_shuf1: db 0, 1, 8, 9, 2, 3, 10, 11, 4, 5, 12, 13, 6, 7, 14, 15
int_shuf2: db 8, 9, 0, 1, 10, 11, 2, 3, 12, 13, 4, 5, 14, 15, 6, 7
int_shuf3: db 0, 1, 8, 9, 4, 5, 12, 13, 2, 3, 10, 11, 6, 7, 14, 15
int_shuf4: db 8, 9, 0, 1, 12, 13, 4, 5, 10, 11, 2, 3, 14, 15, 6, 7
deint_shuf: db 0, 1, 4, 5, 8, 9, 12, 13, 2, 3, 6, 7, 10, 11, 14, 15
int_mshift: db 12, 20, 0, 0, 44, 52, 0, 0
pb_32: times 4 db 32
pw_2048: times 2 dw 2048
pw_4096: times 2 dw 4096
pw_8192: times 2 dw 8192
pw_16384: times 2 dw 16384
pw_1697x16: times 2 dw 1697*16
pw_1697x8: times 2 dw 1697*8
pw_2896x8: times 2 dw 2896*8
pd_2048: dd 2048
%define pw_5 (permD+52)
%define pd_m1 (permD+60)
%define pw_3803_1321 (permD+44)
%define pw_2482_3803 (permD+12)
%define pw_2440_3290 (permD+ 4)
%define pw_m3290_2440 (permD+28)
%define pw_3857_1380 (permD+36)
%define pw_m1380_3857 (permD+20)
pw_8192_m8192: dw 8192, -8192
pw_m8192_8192: dw -8192, 8192
pw_16384_m16384: dw 16384, -16384
pw_m16384_16384: dw -16384, 16384
pw_m1321_2482: dw -1321, 2482
pw_m3344_3344: dw -3344, 3344
pw_2482_3344: dw 2482, 3344
pw_m3803_3344: dw -3803, 3344
pd_3344: dd 3344
pw_m1321_m3344: dw -1321, -3344
pw_2896_m2896: dw 2896, -2896
pw_1567_m3784: dw 1567, -3784
pw_3784_m1567: dw 3784, -1567
pw_4017_m799: dw 4017, -799
pw_2276_m3406: dw 2276, -3406
pw_m799_m4017: dw -799, -4017
pw_m3406_m2276: dw -3406, -2276
%macro COEF_PAIR 2-3 0
pw_%1_%2: dw %1, %2
pw_m%2_%1: dw -%2, %1
%if %3
pw_m%1_m%2: dw -%1, -%2
%endif
%endmacro
COEF_PAIR 2896, 2896
COEF_PAIR 1567, 3784, 1
COEF_PAIR 3784, 1567
COEF_PAIR 201, 4091
COEF_PAIR 995, 3973
COEF_PAIR 1751, 3703
COEF_PAIR 3035, 2751
COEF_PAIR 3513, 2106
COEF_PAIR 4052, 601
COEF_PAIR 3166, 2598, 1
COEF_PAIR 3920, 1189, 1
COEF_PAIR 2276, 3406
COEF_PAIR 4017, 799
%macro COEF_X8 1-*
%rep %0
dw %1*8, %1*8
%rotate 1
%endrep
%endmacro
pw_m2276x8: COEF_X8 -2276
pw_3406x8: COEF_X8 3406
pw_4017x8: COEF_X8 4017
pw_799x8: COEF_X8 799
pw_3784x8: COEF_X8 3784
pw_1567x8: COEF_X8 1567
pw_4076x8: COEF_X8 4076
pw_401x8: COEF_X8 401
pw_m2598x8: COEF_X8 -2598
pw_3166x8: COEF_X8 3166
pw_3612x8: COEF_X8 3612
pw_1931x8: COEF_X8 1931
pw_m1189x8: COEF_X8 -1189
pw_3920x8: COEF_X8 3920
pw_4091x8: COEF_X8 4091
pw_201x8: COEF_X8 201
pw_m2751x8: COEF_X8 -2751
pw_3035x8: COEF_X8 3035
pw_3703x8: COEF_X8 3703
pw_1751x8: COEF_X8 1751
pw_m1380x8: COEF_X8 -1380
pw_3857x8: COEF_X8 3857
pw_3973x8: COEF_X8 3973
pw_995x8: COEF_X8 995
pw_m2106x8: COEF_X8 -2106
pw_3513x8: COEF_X8 3513
pw_3290x8: COEF_X8 3290
pw_2440x8: COEF_X8 2440
pw_m601x8: COEF_X8 -601
pw_4052x8: COEF_X8 4052
pw_401_4076x8: dw 401*8, 4076*8
pw_m2598_3166x8: dw -2598*8, 3166*8
pw_1931_3612x8: dw 1931*8, 3612*8
pw_m1189_3920x8: dw -1189*8, 3920*8
pw_799_4017x8: dw 799*8, 4017*8
pw_m2276_3406x8: dw -2276*8, 3406*8
pw_201_4091x8: dw 201*8, 4091*8
pw_m601_4052x8: dw -601*8, 4052*8
pw_995_3973x8: dw 995*8, 3973*8
pw_m1380_3857x8: dw -1380*8, 3857*8
pw_1751_3703x8: dw 1751*8, 3703*8
pw_m2106_3513x8: dw -2106*8, 3513*8
pw_2440_3290x8: dw 2440*8, 3290*8
pw_m2751_3035x8: dw -2751*8, 3035*8
pw_101_4095x8: dw 101*8, 4095*8
pw_m2824_2967x8: dw -2824*8, 2967*8
pw_1660_3745x8: dw 1660*8, 3745*8
pw_m1474_3822x8: dw -1474*8, 3822*8
pw_897_3996x8: dw 897*8, 3996*8
pw_m2191_3461x8: dw -2191*8, 3461*8
pw_2359_3349x8: dw 2359*8, 3349*8
pw_m700_4036x8: dw -700*8, 4036*8
pw_501_4065x8: dw 501*8, 4065*8
pw_m2520_3229x8: dw -2520*8, 3229*8
pw_2019_3564x8: dw 2019*8, 3564*8
pw_m1092_3948x8: dw -1092*8, 3948*8
pw_1285_3889x8: dw 1285*8, 3889*8
pw_m1842_3659x8: dw -1842*8, 3659*8
pw_2675_3102x8: dw 2675*8, 3102*8
pw_m301_4085x8: dw -301*8, 4085*8
idct64_mul: COEF_X8 4095, 101, 2967, -2824, 3745, 1660, 3822, -1474
COEF_PAIR 401, 4076, 1
COEF_PAIR 799, 4017
COEF_X8 -700, 4036, 2359, 3349, -2191, 3461, 897, 3996
dw -2598, -3166, 3166, -2598, 2598, 3166, -4017, -799, 799, -4017
COEF_X8 4065, 501, 3229, -2520, 3564, 2019, 3948, -1092
COEF_PAIR 1931, 3612, 1
COEF_PAIR 3406, 2276
COEF_X8 -301, 4085, 2675, 3102, -1842, 3659, 1285, 3889
dw -1189, -3920, 3920, -1189, 1189, 3920, -2276, -3406, 3406, -2276
SECTION .text
%define o_base int8_permA+64*18
%define o(x) (r5 - (o_base) + (x))
%define m(x) mangle(private_prefix %+ _ %+ x %+ SUFFIX)
; flags: 1 = swap, 2 = interleave (l), 4 = interleave (t), 8 = no_pack,
; 16 = special_mul1, 32 = special_mul2
%macro ITX_MUL2X_PACK 6-7 0 ; dst/src, tmp[1-2], rnd, coef[1-2], flags
mova m%2, m%4
%if %7 & 16
vpdpwssd m%2, m%1, [o(pw_%5)] {bcstd}
mova m%3, m%4
%if %7 & 32
vpdpwssd m%3, m%1, [o(pw_%6)] {bcstd}
%else
vpdpwssd m%3, m%1, m%6
%endif
%elif %7 & 32
vpdpwssd m%2, m%1, m%5
mova m%3, m%4
vpdpwssd m%3, m%1, [o(pw_%6)] {bcstd}
%elif %6 < 32
vpdpwssd m%2, m%1, m%5
mova m%3, m%4
vpdpwssd m%3, m%1, m%6
%elif %7 & 1
vpdpwssd m%2, m%1, [o(pw_%5_%6)] {bcstd}
mova m%3, m%4
vpdpwssd m%3, m%1, [o(pw_m%6_%5)] {bcstd}
%else
vpdpwssd m%2, m%1, [o(pw_m%6_%5)] {bcstd}
mova m%3, m%4
vpdpwssd m%3, m%1, [o(pw_%5_%6)] {bcstd}
%endif
%if %7 & 2
psrld m%2, 12
pslld m%3, 4
vpshrdd m%1, m%3, m%2, 16
%elif %7 & 4
; compared to using shifts (as above) this has better throughput,
; but worse latency and requires setting up the opmask/index
; registers, so only use this method for the larger transforms
pslld m%1, m%2, 4
vpmultishiftqb m%1{k7}, m13, m%3
%else
psrad m%2, 12
psrad m%3, 12
%if %7 & 8 == 0
packssdw m%1, m%3, m%2
%endif
%endif
%endmacro
; flags: same as ITX_MUL2X_PACK
%macro ITX_MUL4X_PACK 10-11 0 ; dst/src, tmp[1-2], coef_tmp[1-2], rnd, coef[1-4], flags
%if %11 & 1
vpbroadcastd m%4, [o(pw_%9_%10)]
vpbroadcastd m%4{k1}, [o(pw_%7_%8)]
vpbroadcastd m%5, [o(pw_m%10_%9)]
vpbroadcastd m%5{k1}, [o(pw_m%8_%7)]
%else
vpbroadcastd m%4, [o(pw_m%10_%9)]
vpbroadcastd m%4{k1}, [o(pw_m%8_%7)]
vpbroadcastd m%5, [o(pw_%9_%10)]
vpbroadcastd m%5{k1}, [o(pw_%7_%8)]
%endif
ITX_MUL2X_PACK %1, %2, %3, %6, %4, %5, %11
%endmacro
; dst1 = (src1 * coef1 - src2 * coef2 + rnd) >> 12
; dst2 = (src1 * coef2 + src2 * coef1 + rnd) >> 12
%macro ITX_MULSUB_2W 7-8 ; dst/src[1-2], tmp[1-2], rnd, coef[1-2], dst2
punpcklwd m%3, m%2, m%1
punpckhwd m%2, m%1
%if %7 < 32
mova m%1, m%5
vpdpwssd m%1, m%3, m%7
mova m%4, m%5
vpdpwssd m%4, m%2, m%7
%else
mova m%1, m%5
vpdpwssd m%1, m%3, [o(pw_m%7_%6)] {bcstd}
mova m%4, m%5
vpdpwssd m%4, m%2, [o(pw_m%7_%6)] {bcstd}
%endif
psrad m%1, 12
psrad m%4, 12
packssdw m%1, m%4
mova m%4, m%5
%if %7 < 32
vpdpwssd m%4, m%2, m%6
mova m%2, m%5
vpdpwssd m%2, m%3, m%6
%else
vpdpwssd m%4, m%2, [o(pw_%6_%7)] {bcstd}
mova m%2, m%5
vpdpwssd m%2, m%3, [o(pw_%6_%7)] {bcstd}
%endif
psrad m%4, 12
psrad m%2, 12
%if %0 == 8
packssdw m%8, m%2, m%4
%else
packssdw m%2, m%4
%endif
%endmacro
%macro WRAP_XMM 1+
%xdefine %%reset RESET_MM_PERMUTATION
INIT_XMM cpuname
DEFINE_MMREGS xmm
AVX512_MM_PERMUTATION
%1
%%reset
%endmacro
%macro WRAP_YMM 1+
INIT_YMM cpuname
%1
INIT_ZMM cpuname
%endmacro
%macro ITX4_END 4-5 2048 ; row[1-4], rnd
%if %5
vpbroadcastd m2, [o(pw_%5)]
pmulhrsw m0, m2
pmulhrsw m1, m2
%endif
lea r2, [dstq+strideq*2]
%assign %%i 1
%rep 4
%if %1 & 2
CAT_XDEFINE %%row_adr, %%i, r2 + strideq*(%1&1)
%else
CAT_XDEFINE %%row_adr, %%i, dstq + strideq*(%1&1)
%endif
%assign %%i %%i + 1
%rotate 1
%endrep
movd m2, [%%row_adr1]
pinsrd m2, [%%row_adr2], 1
movd m3, [%%row_adr3]
pinsrd m3, [%%row_adr4], 1
pmovzxbw m2, m2
pmovzxbw m3, m3
paddw m0, m2
paddw m1, m3
packuswb m0, m1
movd [%%row_adr1], m0
pextrd [%%row_adr2], m0, 1
pextrd [%%row_adr3], m0, 2
pextrd [%%row_adr4], m0, 3
ret
%endmacro
%macro INV_TXFM_FN 3 ; type1, type2, size
cglobal inv_txfm_add_%1_%2_%3_8bpc, 4, 6, 0, dst, stride, c, eob, tx2, base
%define %%p1 m(i%1_%3_internal_8bpc)
lea baseq, [o_base]
; Jump to the 1st txfm function if we're not taking the fast path, which
; in turn performs an indirect jump to the 2nd txfm function.
lea tx2q, [m(i%2_%3_internal_8bpc).pass2]
%ifidn %1_%2, dct_dct
test eobd, eobd
jnz %%p1
%else
; jump to the 1st txfm function unless it's located directly after this
times ((%%end - %%p1) >> 31) & 1 jmp %%p1
ALIGN function_align
%%end:
%endif
%endmacro
%macro INV_TXFM_4X4_FN 2 ; type1, type2
INV_TXFM_FN %1, %2, 4x4
%ifidn %1_%2, dct_dct
vpbroadcastw m0, [cq]
vpbroadcastd m1, [o(pw_2896x8)]
pmulhrsw m0, m1
mov [cq], eobd
pmulhrsw m0, m1
mova m1, m0
jmp m(iadst_4x4_internal_8bpc).end2
%endif
%endmacro
%macro IDCT4_1D_PACKED 0
vpbroadcastd m4, [o(pd_2048)]
punpckhwd m2, m1, m0
punpcklwd m1, m0
ITX_MUL2X_PACK 2, 0, 3, 4, 1567, 3784
ITX_MUL2X_PACK 1, 0, 3, 4, 2896, 2896
paddsw m0, m1, m2 ; out0 out1
psubsw m1, m2 ; out3 out2
%endmacro
%macro IADST4_1D_PACKED 0
punpcklwd m4, m1, m0 ; in2 in0
punpckhwd m5, m1, m0 ; in3 in1
.main2:
vpbroadcastd m3, [o(pd_2048)]
mova m0, m3
vpdpwssd m0, m4, [o(pw_3803_1321)] {bcstd}
mova m2, m3
vpdpwssd m2, m4, [o(pw_m1321_2482)] {bcstd}
mova m1, m3
vpdpwssd m1, m4, [o(pw_m3344_3344)] {bcstd}
vpdpwssd m3, m4, [o(pw_2482_3803)] {bcstd}
vpdpwssd m0, m5, [o(pw_2482_3344)] {bcstd}
vpdpwssd m2, m5, [o(pw_m3803_3344)] {bcstd}
vpdpwssd m1, m5, [o(pd_3344)] {bcstd}
vpdpwssd m3, m5, [o(pw_m1321_m3344)] {bcstd}
REPX {psrad x, 12}, m0, m2, m1, m3
packssdw m0, m2 ; out0 out1
packssdw m1, m3 ; out2 out3
%endmacro
INIT_XMM avx512icl
INV_TXFM_4X4_FN dct, dct
INV_TXFM_4X4_FN dct, adst
INV_TXFM_4X4_FN dct, flipadst
INV_TXFM_4X4_FN dct, identity
cglobal idct_4x4_internal_8bpc, 0, 6, 0, dst, stride, c, eob, tx2
mova m0, [cq+16*0]
mova m1, [cq+16*1]
IDCT4_1D_PACKED
mova m2, [o(deint_shuf)]
shufps m3, m0, m1, q1331
shufps m0, m0, m1, q0220
pshufb m0, m2
pshufb m1, m3, m2
jmp tx2q
.pass2:
IDCT4_1D_PACKED
pxor ymm16, ymm16
mova [cq], ymm16
ITX4_END 0, 1, 3, 2
INV_TXFM_4X4_FN adst, dct
INV_TXFM_4X4_FN adst, adst
INV_TXFM_4X4_FN adst, flipadst
INV_TXFM_4X4_FN adst, identity
cglobal iadst_4x4_internal_8bpc, 0, 6, 0, dst, stride, c, eob, tx2
mova m0, [cq+16*0]
mova m1, [cq+16*1]
call .main
punpckhwd m3, m0, m1
punpcklwd m0, m1
punpckhwd m1, m0, m3
punpcklwd m0, m3
jmp tx2q
.pass2:
call .main
.end:
pxor ymm16, ymm16
mova [cq], ymm16
.end2:
ITX4_END 0, 1, 2, 3
ALIGN function_align
.main:
IADST4_1D_PACKED
ret
INV_TXFM_4X4_FN flipadst, dct
INV_TXFM_4X4_FN flipadst, adst
INV_TXFM_4X4_FN flipadst, flipadst
INV_TXFM_4X4_FN flipadst, identity
cglobal iflipadst_4x4_internal_8bpc, 0, 6, 0, dst, stride, c, eob, tx2
mova m0, [cq+16*0]
mova m1, [cq+16*1]
call m(iadst_4x4_internal_8bpc).main
punpcklwd m2, m1, m0
punpckhwd m1, m0
punpcklwd m0, m1, m2
punpckhwd m1, m2
jmp tx2q
.pass2:
call m(iadst_4x4_internal_8bpc).main
.end:
pxor ymm16, ymm16
mova [cq], ymm16
.end2:
ITX4_END 3, 2, 1, 0
INV_TXFM_4X4_FN identity, dct
INV_TXFM_4X4_FN identity, adst
INV_TXFM_4X4_FN identity, flipadst
INV_TXFM_4X4_FN identity, identity
cglobal iidentity_4x4_internal_8bpc, 0, 6, 0, dst, stride, c, eob, tx2
mova m0, [cq+16*0]
mova m1, [cq+16*1]
vpbroadcastd m3, [o(pw_1697x8)]
pmulhrsw m2, m3, m0
pmulhrsw m3, m1
paddsw m0, m2
paddsw m1, m3
punpckhwd m2, m0, m1
punpcklwd m0, m1
punpckhwd m1, m0, m2
punpcklwd m0, m2
jmp tx2q
.pass2:
vpbroadcastd m3, [o(pw_1697x8)]
pmulhrsw m2, m3, m0
pmulhrsw m3, m1
paddsw m0, m2
paddsw m1, m3
jmp m(iadst_4x4_internal_8bpc).end
%macro INV_TXFM_4X8_FN 2 ; type1, type2
INV_TXFM_FN %1, %2, 4x8
%ifidn %1_%2, dct_dct
movd xmm1, [o(pw_2896x8)]
pmulhrsw xmm0, xmm1, [cq]
movd xmm2, [o(pw_2048)]
pmulhrsw xmm0, xmm1
pmulhrsw xmm0, xmm1
pmulhrsw xmm0, xmm2
vpbroadcastw ym0, xmm0
mova ym1, ym0
jmp m(iadst_4x8_internal_8bpc).end3
%endif
%endmacro
%macro IDCT8_1D_PACKED 0
punpckhwd m5, m3, m0 ; in7 in1
punpckhwd m4, m1, m2 ; in3 in5
punpcklwd m3, m1 ; in6 in2
punpcklwd m2, m0 ; in4 in0
.main2:
vpbroadcastd m6, [o(pd_2048)]
ITX_MUL2X_PACK 5, 0, 1, 6, 799, 4017, 3 ; t4a t7a
ITX_MUL2X_PACK 4, 0, 1, 6, 3406, 2276, 3 ; t5a t6a
ITX_MUL2X_PACK 3, 0, 1, 6, 1567, 3784 ; t3 t2
psubsw m0, m5, m4 ; t5a t6a (interleaved)
paddsw m4, m5 ; t4 t7 (interleaved)
ITX_MUL2X_PACK 2, 1, 5, 6, 2896, 2896 ; t0 t1
ITX_MUL2X_PACK 0, 1, 5, 6, 2896, 2896, 1 ; t6 t5
%if mmsize > 16
vbroadcasti32x4 m1, [o(deint_shuf)]
pshufb m4, m1
%else
pshufb m4, [o(deint_shuf)]
%endif
psubsw m1, m2, m3 ; tmp3 tmp2
paddsw m3, m2 ; tmp0 tmp1
punpckhqdq m2, m4, m0 ; t7 t6
punpcklqdq m4, m0 ; t4 t5
paddsw m0, m3, m2 ; out0 out1
psubsw m3, m2 ; out7 out6
psubsw m2, m1, m4 ; out4 out5
paddsw m1, m4 ; out3 out2
%endmacro
%macro IADST8_1D_PACKED 1 ; pass
vpbroadcastd m6, [o(pd_2048)]
%if %1 == 1
ITX_MUL2X_PACK 0, 4, 5, 6, 401, 4076, 3 ; t1a t0a
ITX_MUL2X_PACK 1, 4, 5, 6, 1931, 3612, 2 ; t2a t3a
ITX_MUL2X_PACK 2, 4, 5, 6, 3166, 2598, 3 ; t5a t4a
ITX_MUL2X_PACK 3, 4, 5, 6, 3920, 1189, 2 ; t6a t7a
psubsw m4, m0, m2 ; t5 t4
paddsw m0, m2 ; t1 t0
psubsw m5, m1, m3 ; t6 t7
paddsw m1, m3 ; t2 t3
ITX_MUL2X_PACK 4, 2, 3, 6, 1567, 3784, 3 ; t5a t4a
ITX_MUL2X_PACK 5, 2, 3, 6, 3784, 1567, 2 ; t7a t6a
%if mmsize > 16
vbroadcasti32x4 m2, [o(deint_shuf)]
%else
mova m2, [o(deint_shuf)]
%endif
vprord m1, 16
psubsw m3, m0, m1 ; t3 t2
paddsw m0, m1 ; -out7 out0
psubsw m1, m4, m5 ; t7 t6
paddsw m4, m5 ; out6 -out1
pshufb m0, m2
pshufb m4, m2
mova m2, m6
vpdpwssd m2, m3, [o(pw_m2896_2896)] {bcstd}
mova m5, m6
vpdpwssd m5, m1, [o(pw_m2896_2896)] {bcstd}
psrad m2, 12
psrad m5, 12
packssdw m2, m5 ; out4 -out5
mova m5, m6
vpdpwssd m5, m3, [o(pw_2896_2896)] {bcstd}
mova m3, m6
vpdpwssd m3, m1, [o(pw_2896_2896)] {bcstd}
psrad m5, 12
psrad m3, 12
packssdw m1, m3, m5 ; out2 -out3
%else
punpckhwd m0, m4, m3 ; 0 7
punpckhwd m1, m5, m2 ; 2 5
punpcklwd m2, m5 ; 4 3
punpcklwd m3, m4 ; 6 1
ITX_MUL2X_PACK 0, 4, 5, 6, 401, 4076 ; t0a t1a
ITX_MUL2X_PACK 1, 4, 5, 6, 1931, 3612 ; t2a t3a
ITX_MUL2X_PACK 2, 4, 5, 6, 3166, 2598 ; t4a t5a
ITX_MUL2X_PACK 3, 4, 5, 6, 3920, 1189 ; t6a t7a
psubsw m4, m0, m2 ; t4 t5
paddsw m0, m2 ; t0 t1
psubsw m5, m1, m3 ; t6 t7
paddsw m1, m3 ; t2 t3
shufps m2, m5, m4, q1032
punpckhwd m4, m2
punpcklwd m5, m2
ITX_MUL2X_PACK 4, 2, 3, 6, 1567, 3784 ; t4a t5a
ITX_MUL2X_PACK 5, 2, 3, 6, 3784, 1567, 1 ; t6a t7a
psubsw m2, m0, m1 ; t2 t3
paddsw m0, m1 ; out0 -out7
psubsw m1, m4, m5 ; t6 t7
paddsw m4, m5 ; -out1 out6
vpbroadcastd m5, [o(pw_2896x8)]
punpckhqdq m3, m2, m1 ; t3 t7
punpcklqdq m2, m1 ; t2 t6
paddsw m1, m2, m3 ; t2+t3 t6+t7
psubsw m2, m3 ; t2-t3 t6-t7
punpckhqdq m3, m4, m0 ; out6 -out7
punpcklqdq m0, m4 ; out0 -out1
pmulhrsw m2, m5 ; out4 -out5
pshufd m1, m1, q1032
pmulhrsw m1, m5 ; out2 -out3
%endif
%endmacro
INIT_YMM avx512icl
INV_TXFM_4X8_FN dct, dct
INV_TXFM_4X8_FN dct, identity
INV_TXFM_4X8_FN dct, adst
INV_TXFM_4X8_FN dct, flipadst
cglobal idct_4x8_internal_8bpc, 0, 6, 0, dst, stride, c, eob, tx2
vpermq m0, [cq+32*0], q3120
vpermq m1, [cq+32*1], q3120
vpbroadcastd m2, [o(pw_2896x8)]
pmulhrsw m0, m2
pmulhrsw m1, m2
IDCT4_1D_PACKED
vbroadcasti32x4 m2, [o(deint_shuf)]
shufps m3, m0, m1, q1331
shufps m0, m0, m1, q0220
pshufb m0, m2
pshufb m1, m3, m2
jmp tx2q
.pass2:
vextracti32x4 xm2, m0, 1
vextracti32x4 xm3, m1, 1
call .main
vpbroadcastd m4, [o(pw_2048)]
vinserti32x4 m0, m0, xm2, 1
vinserti32x4 m1, m1, xm3, 1
pshufd m1, m1, q1032
jmp m(iadst_4x8_internal_8bpc).end2
ALIGN function_align
.main:
WRAP_XMM IDCT8_1D_PACKED
ret
INV_TXFM_4X8_FN adst, dct
INV_TXFM_4X8_FN adst, adst
INV_TXFM_4X8_FN adst, flipadst
INV_TXFM_4X8_FN adst, identity
cglobal iadst_4x8_internal_8bpc, 0, 6, 0, dst, stride, c, eob, tx2
vpermq m0, [cq+32*0], q3120
vpermq m1, [cq+32*1], q3120
vpbroadcastd m2, [o(pw_2896x8)]
pmulhrsw m0, m2
pmulhrsw m1, m2
call m(iadst_8x4_internal_8bpc).main
punpckhwd m3, m0, m1
punpcklwd m0, m1
punpckhwd m1, m0, m3
punpcklwd m0, m3
jmp tx2q
.pass2:
vextracti32x4 xm2, m0, 1
vextracti32x4 xm3, m1, 1
pshufd xm4, xm0, q1032
pshufd xm5, xm1, q1032
call .main_pass2
vpbroadcastd m4, [o(pw_2048)]
vinserti32x4 m0, xm2, 1
vinserti32x4 m1, xm3, 1
pxor m5, m5
psubw m5, m4
.end:
punpcklqdq m4, m5
.end2:
pmulhrsw m0, m4
pmulhrsw m1, m4
.end3:
vpbroadcastd m3, strided
pmulld m5, m3, [o(pd_0to15)]
kxnorb k1, k1, k1
kmovb k2, k1
vpgatherdd m3{k1}, [dstq+m5]
pxor m4, m4
mova [cq], zmm20
punpcklbw m2, m3, m4
punpckhbw m3, m4
paddw m0, m2
paddw m1, m3
packuswb m0, m1
vpscatterdd [dstq+m5]{k2}, m0
RET
ALIGN function_align
.main_pass1:
punpckhwd xm0, xm4, xm3 ; 0 7
punpckhwd xm1, xm5, xm2 ; 2 5
punpcklwd xm2, xm5 ; 4 3
punpcklwd xm3, xm4 ; 6 1
WRAP_XMM IADST8_1D_PACKED 1
punpcklqdq xm3, xm4, xm0 ; out6 -out7
punpckhqdq xm0, xm4 ; out0 -out1
ret
ALIGN function_align
.main_pass2:
WRAP_XMM IADST8_1D_PACKED 2
ret
INV_TXFM_4X8_FN flipadst, dct
INV_TXFM_4X8_FN flipadst, adst
INV_TXFM_4X8_FN flipadst, flipadst
INV_TXFM_4X8_FN flipadst, identity
cglobal iflipadst_4x8_internal_8bpc, 0, 6, 0, dst, stride, c, eob, tx2
vpermq m0, [cq+32*0], q3120
vpermq m1, [cq+32*1], q3120
vpbroadcastd m2, [o(pw_2896x8)]
pmulhrsw m0, m2
pmulhrsw m1, m2
call m(iadst_8x4_internal_8bpc).main
punpcklwd m3, m1, m0
punpckhwd m1, m0
punpcklwd m0, m1, m3
punpckhwd m1, m3
jmp tx2q
.pass2:
vextracti32x4 xm2, m0, 1
vextracti32x4 xm3, m1, 1
pshufd xm4, xm0, q1032
pshufd xm5, xm1, q1032
call m(iadst_4x8_internal_8bpc).main_pass2
vpbroadcastd m5, [o(pw_2048)]
vinserti32x4 m3, xm1, 1
vinserti32x4 m2, xm0, 1
pxor m4, m4
psubw m4, m5
pshufd m0, m3, q1032
pshufd m1, m2, q1032
jmp m(iadst_4x8_internal_8bpc).end
INIT_ZMM avx512icl
INV_TXFM_4X8_FN identity, dct
INV_TXFM_4X8_FN identity, adst
INV_TXFM_4X8_FN identity, flipadst
INV_TXFM_4X8_FN identity, identity
cglobal iidentity_4x8_internal_8bpc, 0, 6, 0, dst, stride, c, eob, tx2
vpbroadcastd m0, [o(pw_2896x8)]
pmulhrsw m0, [cq]
mova m1, [o(int8_permB)]
vpbroadcastd m2, [o(pw_1697x8)]
vpermb m0, m1, m0
pmulhrsw m2, m0
paddsw m0, m2
vextracti32x8 ym1, m0, 1
jmp tx2q
.pass2:
vpbroadcastd ym4, [o(pw_4096)]
jmp m(iadst_4x8_internal_8bpc).end2
%macro INV_TXFM_4X16_FN 2 ; type1, type2
INV_TXFM_FN %1, %2, 4x16
%ifidn %1_%2, dct_dct
movsx r6d, word [cq]
mov [cq], eobd
imul r6d, 181
add r6d, 128+256
sar r6d, 8+1
imul r6d, 181
add r6d, 128+2048
sar r6d, 8+4
vpbroadcastw m0, r6d
mova m1, m0
jmp m(iadst_4x16_internal_8bpc).end3
%endif
%endmacro
%macro IDCT16_1D_PACKED 0
punpckhwd m8, m7, m0 ; dct16 in15 in1
punpcklwd m9, m4, m0 ; dct4 in2 in0
punpckhwd m0, m3, m4 ; dct16 in7 in9
punpcklwd m7, m1 ; dct8 in7 in1
punpckhwd m1, m6 ; dct16 in3 in13
punpcklwd m3, m5 ; dct8 in3 in5
punpckhwd m5, m2 ; dct16 in11 in5
punpcklwd m6, m2 ; dct4 in3 in1
cglobal_label .main2
vpbroadcastd m10, [o(pd_2048)]
.main3:
vpbroadcastq m13, [o(int_mshift)]
vpcmpub k7, m13, m10, 6 ; 0x33...
ITX_MUL2X_PACK 8, 2, 4, 10, 401, 4076, 5 ; t8a t15a
ITX_MUL2X_PACK 0, 2, 4, 10, 3166, 2598, 5 ; t9a t14a
ITX_MUL2X_PACK 5, 2, 4, 10, 1931, 3612, 5 ; t10a t13a
ITX_MUL2X_PACK 1, 2, 4, 10, 3920, 1189, 5 ; t11a t12a
ITX_MUL2X_PACK 7, 2, 4, 10, 799, 4017, 5 ; t4a t7a
ITX_MUL2X_PACK 3, 2, 4, 10, 3406, 2276, 5 ; t5a t6a
.main4:
psubsw m2, m8, m0 ; t9 t14
paddsw m8, m0 ; t8 t15
psubsw m4, m1, m5 ; t10 t13
paddsw m1, m5 ; t11 t12
ITX_MUL2X_PACK 6, 0, 5, 10, 1567, 3784 ; t3 t2
psubsw m0, m8, m1 ; t11a t12a
paddsw m8, m1 ; t8a t15a
psubsw m1, m7, m3 ; t5a t6a
paddsw m7, m3 ; t4 t7
.main5:
ITX_MUL2X_PACK 2, 3, 5, 10, 1567, 3784, 5 ; t9a t14a
ITX_MUL2X_PACK 4, 3, 5, 10, m3784, 1567, 5 ; t10a t13a
%if mmsize > 16
vbroadcasti32x4 m5, [o(deint_shuf)]
%else
mova m5, [o(deint_shuf)]
%endif
vpbroadcastd m11, [o(pw_m2896_2896)]
vpbroadcastd m12, [o(pw_2896_2896)]
paddsw m3, m2, m4 ; t9 t14
psubsw m2, m4 ; t10 t13
pshufb m8, m5
pshufb m7, m5
pshufb m3, m5
ITX_MUL2X_PACK 9, 4, 5, 10, 11, 12 ; t0 t1
ITX_MUL2X_PACK 1, 4, 5, 10, 12, 11 ; t5 t6
ITX_MUL2X_PACK 0, 4, 5, 10, 11, 12, 8 ; t11 t12
ITX_MUL2X_PACK 2, 0, 11, 10, 11, 12, 8 ; t10a t13a
punpckhqdq m2, m7, m1 ; t7 t6
punpcklqdq m7, m1 ; t4 t5
psubsw m1, m9, m6 ; dct4 out3 out2
paddsw m9, m6 ; dct4 out0 out1
packssdw m5, m11 ; t12 t13a
packssdw m4, m0 ; t11 t10a
punpckhqdq m0, m8, m3 ; t15a t14
punpcklqdq m8, m3 ; t8a t9
psubsw m3, m9, m2 ; dct8 out7 out6
paddsw m9, m2 ; dct8 out0 out1
psubsw m2, m1, m7 ; dct8 out4 out5
paddsw m1, m7 ; dct8 out3 out2
psubsw m7, m9, m0 ; out15 out14
paddsw m0, m9 ; out0 out1
psubsw m6, m1, m5 ; out12 out13
paddsw m1, m5 ; out3 out2
psubsw m5, m2, m4 ; out11 out10
paddsw m2, m4 ; out4 out5
psubsw m4, m3, m8 ; out8 out9
paddsw m3, m8 ; out7 out6
%endmacro
INV_TXFM_4X16_FN dct, dct
INV_TXFM_4X16_FN dct, identity
INV_TXFM_4X16_FN dct, adst
INV_TXFM_4X16_FN dct, flipadst
cglobal idct_4x16_internal_8bpc, 0, 6, 0, dst, stride, c, eob, tx2
mova ym1, [cq+32*2]
vinserti32x8 m1, [cq+32*0], 1
mova m0, [o(int16_perm)]
mova ym2, [cq+32*3]
vinserti32x8 m2, [cq+32*1], 1
vpbroadcastd m4, [o(pd_2048)]
vpermb m1, m0, m1 ; c0 a0 c1 a1 c2 a2 c3 a3
vpermb m2, m0, m2 ; d0 b0 d1 b1 d2 b2 d3 b3
ITX_MUL2X_PACK 1, 0, 3, 4, 2896, 2896, 2
ITX_MUL2X_PACK 2, 0, 3, 4, 1567, 3784, 2
vpbroadcastd m4, [o(pw_16384)]
psubsw m3, m1, m2
paddsw m1, m2 ; out0 out1
vprord m3, 16 ; out2 out3
punpckldq m0, m1, m3
punpckhdq m1, m3
pmulhrsw m0, m4
pmulhrsw m1, m4
jmp tx2q
.pass2:
vextracti32x4 xm2, ym0, 1
vextracti32x4 xm3, ym1, 1
vextracti32x4 xm4, m0, 2
vextracti32x4 xm5, m1, 2
vextracti32x4 xm6, m0, 3
vextracti32x4 xm7, m1, 3
call .main
vinserti32x4 ym0, xm2, 1
vinserti32x4 ym1, xm3, 1
vinserti32x4 ym4, xm6, 1
vinserti32x4 ym5, xm7, 1
vinserti32x8 m0, ym4, 1
vinserti32x8 m1, ym5, 1
vpbroadcastd m5, [o(pw_2048)]
pshufd m1, m1, q1032
jmp m(iadst_4x16_internal_8bpc).end2
ALIGN function_align
.main:
WRAP_XMM IDCT16_1D_PACKED
ret
INV_TXFM_4X16_FN adst, dct
INV_TXFM_4X16_FN adst, adst
INV_TXFM_4X16_FN adst, flipadst
INV_TXFM_4X16_FN adst, identity
cglobal iadst_4x16_internal_8bpc, 0, 6, 0, dst, stride, c, eob, tx2
mova m1, [o(permB)]
vpermq m0, m1, [cq+64*0]
vpermq m1, m1, [cq+64*1]
call m(iadst_16x4_internal_8bpc).main
vpbroadcastd m3, [o(pw_16384)]
punpckhwd m2, m0, m1
punpcklwd m0, m1
pmulhrsw m2, m3
pmulhrsw m0, m3
punpckhwd m1, m0, m2
punpcklwd m0, m2
jmp tx2q
.pass2:
call .main
vpbroadcastd m5, [o(pw_2048)]
psrlq m10, 4
psubw m6, m8, m5
.end:
vpbroadcastd m7, [o(pw_2896x8)]
paddsw ym1, ym2, ym4
psubsw ym2, ym4
vinserti32x8 m1, ym2, 1
pmulhrsw m1, m7 ; -out7 out4 out6 -out5 out8 -out11 -out9 out10
psrlq m0, m10, 4
vpermi2q m0, m1, m3 ; 0 1 4 5 8 9 c d
vpermt2q m1, m10, m3 ; 2 3 6 7 a b e f
punpcklqdq m5, m6
.end2:
pmulhrsw m0, m5
pmulhrsw m1, m5
.end3:
vpbroadcastd m3, strided
pmulld m5, m3, [o(pd_0to15)]
kxnorw k1, k1, k1
kmovw k2, k1
vpgatherdd m3{k1}, [dstq+m5]