Trivial bootstrap for Linux kernel for test SoC

Author: ultraembedded

boot.S

@@ -0,0 +1,142 @@
+#####################################################
+# Entry point
+#####################################################
+.org    0x0
+boot_vector:
+	j start
+
+#####################################################
+# ISR Vector
+#####################################################
+.org    0x20
+.global isr_vector
+isr_vector:
+    csrrw sp, mscratch, sp
+    addi sp, sp, -(35*4)
+
+    # Save registers
+    sw x31, (4*34)(sp)
+    sw x30, (4*33)(sp)
+    sw x29, (4*32)(sp)
+    sw x28, (4*31)(sp)
+    sw x27, (4*30)(sp)
+    sw x26, (4*29)(sp)
+    sw x25, (4*28)(sp)
+    sw x24, (4*27)(sp)
+    sw x23, (4*26)(sp)
+    sw x22, (4*25)(sp)
+    sw x21, (4*24)(sp)
+    sw x20, (4*23)(sp)
+    sw x19, (4*22)(sp)
+    sw x18, (4*21)(sp)
+    sw x17, (4*20)(sp)
+    sw x16, (4*19)(sp)
+    sw x15, (4*18)(sp)
+    sw x14, (4*17)(sp)
+    sw x13, (4*16)(sp)
+    sw x12, (4*15)(sp)
+    sw x11, (4*14)(sp)
+    sw x10, (4*13)(sp)
+    sw x9,  (4*12)(sp)
+    sw x8,  (4*11)(sp)
+    sw x7,  (4*10)(sp)
+    sw x6,  (4* 9)(sp)
+    sw x5,  (4* 8)(sp)
+    sw x4,  (4* 7)(sp)
+    sw x3,  (4* 6)(sp)
+    sw x2,  (4* 5)(sp) # SP
+    sw x1,  (4* 4)(sp) # RA
+
+    csrr s0, mcause
+    sw s0,  (4* 2)(sp)
+
+    csrr s0, mstatus
+    sw s0,  (4* 1)(sp)
+
+    csrr s0, mepc
+    sw s0,  (4* 0)(sp)
+
+    # Call ISR handler
+    mv a0, sp
+    jal exception_handler
+    mv sp, a0
+
+    # Restore registers
+    lw s0,  (4* 0)(sp)
+    csrw mepc, s0
+
+    lw s0,  (4* 1)(sp)
+    csrw mstatus, s0
+
+    lw x1,  (4* 4)(sp)
+    lw x3,  (4* 6)(sp)
+    lw x4,  (4* 7)(sp)
+    lw x5,  (4* 8)(sp)
+    lw x6,  (4* 9)(sp)
+    lw x7,  (4*10)(sp)
+    lw x8,  (4*11)(sp)
+    lw x9,  (4*12)(sp)
+    lw x10, (4*13)(sp)
+    lw x11, (4*14)(sp)
+    lw x12, (4*15)(sp)
+    lw x13, (4*16)(sp)
+    lw x14, (4*17)(sp)
+    lw x15, (4*18)(sp)
+    lw x16, (4*19)(sp)
+    lw x17, (4*20)(sp)
+    lw x18, (4*21)(sp)
+    lw x19, (4*22)(sp)
+    lw x20, (4*23)(sp)
+    lw x21, (4*24)(sp)
+    lw x22, (4*25)(sp)
+    lw x23, (4*26)(sp)
+    lw x24, (4*27)(sp)
+    lw x25, (4*28)(sp)
+    lw x26, (4*29)(sp)
+    lw x27, (4*30)(sp)
+    lw x28, (4*31)(sp)
+    lw x29, (4*32)(sp)
+    lw x30, (4*33)(sp)
+    lw x31, (4*34)(sp)
+
+    addi sp, sp, (35*4)
+    csrrw sp, mscratch, sp
+    mret
+
+#####################################################
+# Start
+#####################################################
+start:
+    # Setup stack pointer
+    lui sp, %hi(_sp)
+    add sp, sp, %lo(_sp)
+
+    # Setup IRQ vector
+    lui t0, %hi(isr_vector)
+    add t0, t0, %lo(isr_vector)
+    csrw mtvec, t0
+
+    # t0 = _bss_start
+    lui t0,%hi(_bss_start)
+    add t0,t0,%lo(_bss_start)
+    
+    # t1 = _end
+    lui t1,%hi(_end)
+    add t1,t1,%lo(_end)
+
+bss_clear:
+    sw x0,  (0)(t0)        # Write 0x00 to mem[t0]
+    add t0, t0, 4          # t0 += 4
+    blt t0, t1, bss_clear  # Branch back to bss_clear if (t0 < t1)
+
+    # Run main
+    jal main
+
+#####################################################
+# Exit
+#####################################################
+.global _exit
+_exit:
+    csrw dscratch, x0
+_exit_loop:
+    jal _exit_loop

csr.h

@@ -0,0 +1,31 @@
+#ifndef __CSR_H__
+#define __CSR_H__
+
+#include <stdint.h>
+
+//-----------------------------------------------------------------
+// Defines:
+//-----------------------------------------------------------------
+#define MSTATUS_MPP_SHIFT   11
+#define PRV_S 1
+#define PRV_M 3
+
+//-----------------------------------------------------------------
+// Helpers:
+//-----------------------------------------------------------------
+#define csr_read(reg) ({ unsigned long __tmp; \
+  asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+  __tmp; })
+
+#define csr_write(reg, val) ({ \
+  asm volatile ("csrw " #reg ", %0" :: "rK"(val)); })
+
+#define csr_set(reg, bit) ({ unsigned long __tmp; \
+  asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
+  __tmp; })
+
+#define csr_clear(reg, bit) ({ unsigned long __tmp; \
+  asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
+  __tmp; })
+
+#endif

custom.ld

@@ -0,0 +1,63 @@
+GROUP("libgcc.a")
+
+MEMORY
+{
+  sram (rwx) : ORIGIN = BASE_ADDRESS, LENGTH = 31M
+  rom (r)    : ORIGIN = BASE_ADDRESS + 0x1F00000, LENGTH = 1M
+}
+
+SECTIONS
+{   
+    /* first section is .text which is used for code */
+    .text :
+    {
+        *(.text .text.*)           /* remaining code */
+        *(.rodata)                 /* read-only data (constants) */
+        *(.rodata*)
+        *(.rdata*)
+        . = ALIGN(4);
+    } > sram
+
+    /* .data section which is used for initialized data */
+    .data : 
+    {
+    *(.got.plt) *(.got)
+    *(.shdata)
+    *(.data .data.* .gnu.linkonce.d.*)
+    . = ALIGN(16);
+    *(.lit8)
+    *(.lit4)
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+    . = ALIGN (8);
+    *(.ram)
+    . = ALIGN (8);
+    _edata = .;
+    } > sram    
+     
+  .bss : 
+  {
+    . = ALIGN(4);
+    _bss_start = . ;
+    
+    *(.bss*)
+    *(.sbss*)
+    *(COMMON)
+    /* Allocate room for stack */
+    .   =  ALIGN(8) ;
+    .   += 4096 ;
+    _sp =  . - 16;
+  } > sram
+
+  . = ALIGN(4);
+  _end = . ;
+
+  .payload :
+  {
+    *(.payload)
+  }  
+
+  .dtb :
+  {
+    *(.dtb)
+  } > rom
+}

exception.c

@@ -0,0 +1,40 @@
+#include "exception.h"
+#include "csr.h"
+#include "serial.h"
+
+//-----------------------------------------------------------------
+// Locals
+//-----------------------------------------------------------------
+#define CAUSE_MAX_EXC      (CAUSE_PAGE_FAULT_STORE + 1)
+static fp_exception        _exception_table[CAUSE_MAX_EXC];
+
+//-----------------------------------------------------------------
+// exception_set_handler: Register exception handler
+//-----------------------------------------------------------------
+void exception_set_handler(int cause, fp_exception handler)
+{
+    _exception_table[cause] = handler;
+}
+//-----------------------------------------------------------------
+// exception_handler:
+//-----------------------------------------------------------------
+struct irq_context * exception_handler(struct irq_context *ctx)
+{
+    switch (ctx->cause)
+    {
+        case CAUSE_ECALL_U:
+        case CAUSE_ECALL_S:
+        case CAUSE_ECALL_M:
+            ctx->pc += 4;
+            break;
+    }
+
+    if (ctx->cause < CAUSE_MAX_EXC && _exception_table[ctx->cause])
+        ctx = _exception_table[ctx->cause](ctx);
+    else
+    {
+        serial_putstr("Unhandled exception, stopping...\n");
+        _exit(-1);
+    }
+    return ctx;
+}

exception.h

@@ -0,0 +1,53 @@
+#ifndef __EXCEPTION_H__
+#define __EXCEPTION_H__
+
+#include <stdint.h>
+
+//-----------------------------------------------------------------
+// Defines:
+//-----------------------------------------------------------------
+#define REG_RA                         1
+#define REG_SP                         2
+#define REG_ARG0                       10
+#define REG_RET                        REG_ARG0
+#define NUM_GP_REG                     32
+#define NUM_CSR_REG                    3
+
+#define CAUSE_MISALIGNED_FETCH         0
+#define CAUSE_FAULT_FETCH              1
+#define CAUSE_ILLEGAL_INSTRUCTION      2
+#define CAUSE_BREAKPOINT               3
+#define CAUSE_MISALIGNED_LOAD          4
+#define CAUSE_FAULT_LOAD               5
+#define CAUSE_MISALIGNED_STORE         6
+#define CAUSE_FAULT_STORE              7
+#define CAUSE_ECALL_U                  8
+#define CAUSE_ECALL_S                  9
+#define CAUSE_ECALL_M                  11
+#define CAUSE_PAGE_FAULT_INST          12
+#define CAUSE_PAGE_FAULT_LOAD          13
+#define CAUSE_PAGE_FAULT_STORE         15
+#define CAUSE_INTERRUPT                (1 << 31)
+
+//-----------------------------------------------------------------
+// Types:
+//-----------------------------------------------------------------
+struct irq_context
+{
+    uint32_t pc;
+    uint32_t status;
+    uint32_t cause;
+    uint32_t reg[NUM_GP_REG];
+};
+
+typedef struct irq_context *(*fp_exception)(struct irq_context *ctx);
+
+//-----------------------------------------------------------------
+// Prototypes:
+//-----------------------------------------------------------------
+struct irq_context * exception_handler(struct irq_context *ctx);
+void                 exception_set_handler(int cause, fp_exception handler);
+extern void          _exit(int arg);
+
+#endif
+

main.c

@@ -0,0 +1,55 @@
+#include <stdint.h>
+#include "csr.h"
+#include "exception.h"
+#include "syscalls.h"
+#include "serial.h"
+
+//-----------------------------------------------------------------
+// Defines:
+//-----------------------------------------------------------------
+#define SERIAL_BASE        0x92000000
+
+//-----------------------------------------------------------------
+// Globals:
+//-----------------------------------------------------------------
+extern uint32_t _payload_start;
+extern uint32_t _dtb_start;
+extern uint32_t _sp;
+
+//-----------------------------------------------------------------
+// main:
+//-----------------------------------------------------------------
+int main(void)
+{
+    uint32_t entry_addr = (uint32_t)&_payload_start;
+    uint32_t dtb_addr   = (uint32_t)&_dtb_start;   
+
+    // Setup serial port
+    serial_init(SERIAL_BASE, 0 /* NOT USED */);
+    serial_putstr("Booting...\n");
+
+    // Register fault handlers
+    exception_set_handler(CAUSE_ECALL_S, handle_syscall);
+
+    // Boot kernel
+    csr_write(mstatus, PRV_S << MSTATUS_MPP_SHIFT);
+
+    // Configure interrupt / exception delegation
+    // Delegate everything except super/machine level syscalls
+    csr_write(medeleg, ~(1 << CAUSE_ECALL_S));
+    csr_write(mideleg, ~0);
+
+    // Boot target
+    csr_write(mepc, entry_addr);
+
+    // Set machine mode exception stack
+    csr_write(mscratch, &_sp);
+
+    // Switch from machine mode to supervisor mode
+    register uintptr_t a0 asm ("a0") = 0;
+    register uintptr_t a1 asm ("a1") = dtb_addr;
+    asm volatile ("mret" : : "r" (a0), "r" (a1));
+
+    return 0;
+}
+