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greyroguegreyrogue
authoredNov 13, 2024
Merge pull request MiSTer-devel#2 from greyrogue/rework_sys
update sys
·
v0.120250314
2 parents 2ab6b66 + e66789a commit 8acfe0f

25 files changed

+6601
-4982
lines changed
 

‎Jaguar.sv

+8-4
Original file line numberDiff line numberDiff line change
@@ -57,13 +57,15 @@ module emu
5757
output VGA_F1,
5858
output [1:0] VGA_SL,
5959
output VGA_SCALER, // Force VGA scaler
60+
output VGA_DISABLE, // analog out is off
6061

6162
input [11:0] HDMI_WIDTH,
6263
input [11:0] HDMI_HEIGHT,
6364
output HDMI_FREEZE,
65+
output HDMI_BLACKOUT,
6466

6567
`ifdef MISTER_FB
66-
// Use framebuffer in DDRAM (USE_FB=1 in qsf)
68+
// Use framebuffer in DDRAM
6769
// FB_FORMAT:
6870
// [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp
6971
// [3] : 0=16bits 565 1=16bits 1555
@@ -187,7 +189,9 @@ assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
187189
assign VGA_SL = 0;
188190
assign VGA_F1 = 0;
189191
assign VGA_SCALER = 0;
192+
assign VGA_DISABLE = 0;
190193
assign HDMI_FREEZE = 0;
194+
assign HDMI_BLACKOUT = 0;
191195

192196
assign LED_DISK = 0;
193197
assign LED_POWER = 0;
@@ -235,7 +239,7 @@ assign VIDEO_ARY = (!ar) ? 12'd2040 : 12'd0;
235239
// 0123456789ABCDEFGHIJKLMNOPQRSTUV 0123456789ABCDEFGHIJKLMNOPQRSTUV
236240
// X XXXXXXX
237241

238-
//
242+
//
239243

240244
`include "build_id.v"
241245
localparam CONF_STR = {
@@ -540,7 +544,7 @@ assign CLK_VIDEO = clk_sys;
540544

541545
//assign VGA_SL = {~interlace,~interlace} & sl[1:0];
542546

543-
video_mixer #(.LINE_LENGTH(1410), .HALF_DEPTH(0), .GAMMA(1)) video_mixer
547+
video_mixer #(.LINE_LENGTH(700), .HALF_DEPTH(0), .GAMMA(1)) video_mixer
544548
(
545549
.CLK_VIDEO(CLK_VIDEO), // input clk_sys
546550
.ce_pix( vid_ce ), // input ce_pix
@@ -589,7 +593,7 @@ assign DDRAM_BURSTCNT = 1;
589593
// The cart ROM is loaded at 0x30800000, as the Jag normally expects the cart to be mapped at offset 0x800000.
590594
// DRAM address is using "abus_out" here (byte address, so three LSB bits are ignored!)
591595
// so the MSB bit [23] will be set by the Jag core when reading the cart at 0x800000. TODO - confirm this is always the case!
592-
assign DDRAM_ADDR = (loader_en) ? {8'b0110000, loader_addr[23:3]} : {8'b0110000, abus_out[23:3]};
596+
assign DDRAM_ADDR = (loader_en) ? {8'b0110000, loader_addr[23:3]} : {8'b0110000, abus_out[23:3]};
593597
assign DDRAM_RD = (loader_en) ? 1'b0 : cart_rd_trig;
594598
assign DDRAM_WE = (loader_en) ? loader_wr : 1'b0;
595599

‎Jaguar_Rework.qsf

+1,313-1,302
Large diffs are not rendered by default.

‎sys/arcade_video.v

+5
Original file line numberDiff line numberDiff line change
@@ -99,6 +99,11 @@ generate
9999
assign G = {RGB_fix[7:4],RGB_fix[7:4]};
100100
assign B = {RGB_fix[3:0],RGB_fix[3:0]};
101101
end
102+
else if(DW == 18) begin
103+
assign R = {RGB_fix[17:12],RGB_fix[17:16]};
104+
assign G = {RGB_fix[11: 6],RGB_fix[11:10]};
105+
assign B = {RGB_fix[ 5: 0],RGB_fix[ 5: 4]};
106+
end
102107
else begin // 24
103108
assign R = RGB_fix[23:16];
104109
assign G = RGB_fix[15:8];

‎sys/ascal.vhd

+2,800-2,743
Large diffs are not rendered by default.

‎sys/hdmi_config.sv

-239
This file was deleted.

‎sys/hps_io.sv

+112-53
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@
2727
// VDNUM 1..10
2828
// BLKSZ 0..7: 0 = 128, 1 = 256, 2 = 512(default), .. 7 = 16384
2929
//
30-
module hps_io #(parameter CONF_STR, CONF_STR_BRAM=1, PS2DIV=0, WIDE=0, VDNUM=1, BLKSZ=2, PS2WE=0)
30+
module hps_io #(parameter CONF_STR, CONF_STR_BRAM=0, PS2DIV=0, WIDE=0, VDNUM=1, BLKSZ=2, PS2WE=0, STRLEN=$size(CONF_STR)>>3)
3131
(
3232
input clk_sys,
3333
inout [48:0] HPS_BUS,
@@ -39,7 +39,7 @@ module hps_io #(parameter CONF_STR, CONF_STR_BRAM=1, PS2DIV=0, WIDE=0, VDNUM=1,
3939
output reg [31:0] joystick_3,
4040
output reg [31:0] joystick_4,
4141
output reg [31:0] joystick_5,
42-
42+
4343
// analog -127..+127, Y: [15:8], X: [7:0]
4444
output reg [15:0] joystick_l_analog_0,
4545
output reg [15:0] joystick_l_analog_1,
@@ -55,6 +55,13 @@ module hps_io #(parameter CONF_STR, CONF_STR_BRAM=1, PS2DIV=0, WIDE=0, VDNUM=1,
5555
output reg [15:0] joystick_r_analog_4,
5656
output reg [15:0] joystick_r_analog_5,
5757

58+
input [15:0] joystick_0_rumble, // 15:8 - 'large' rumble motor magnitude, 7:0 'small' rumble motor magnitude
59+
input [15:0] joystick_1_rumble,
60+
input [15:0] joystick_2_rumble,
61+
input [15:0] joystick_3_rumble,
62+
input [15:0] joystick_4_rumble,
63+
input [15:0] joystick_5_rumble,
64+
5865
// paddle 0..255
5966
output reg [7:0] paddle_0,
6067
output reg [7:0] paddle_1,
@@ -71,6 +78,29 @@ module hps_io #(parameter CONF_STR, CONF_STR_BRAM=1, PS2DIV=0, WIDE=0, VDNUM=1,
7178
output reg [8:0] spinner_4,
7279
output reg [8:0] spinner_5,
7380

81+
// ps2 keyboard emulation
82+
output ps2_kbd_clk_out,
83+
output ps2_kbd_data_out,
84+
input ps2_kbd_clk_in,
85+
input ps2_kbd_data_in,
86+
87+
input [2:0] ps2_kbd_led_status,
88+
input [2:0] ps2_kbd_led_use,
89+
90+
output ps2_mouse_clk_out,
91+
output ps2_mouse_data_out,
92+
input ps2_mouse_clk_in,
93+
input ps2_mouse_data_in,
94+
95+
// ps2 alternative interface.
96+
97+
// [8] - extended, [9] - pressed, [10] - toggles with every press/release
98+
output reg [10:0] ps2_key = 0,
99+
100+
// [24] - toggles with every event
101+
output reg [24:0] ps2_mouse = 0,
102+
output reg [15:0] ps2_mouse_ext = 0, // 15:8 - reserved(additional buttons), 7:0 - wheel movements
103+
74104
output [1:0] buttons,
75105
output forced_scandoubler,
76106
output direct_video,
@@ -79,10 +109,12 @@ module hps_io #(parameter CONF_STR, CONF_STR_BRAM=1, PS2DIV=0, WIDE=0, VDNUM=1,
79109
//toggle to force notify of video mode change
80110
input new_vmode,
81111

82-
output reg [63:0] status,
83-
input [63:0] status_in,
84-
input status_set,
85-
input [15:0] status_menumask,
112+
inout [21:0] gamma_bus,
113+
114+
output reg [127:0] status,
115+
input [127:0] status_in,
116+
input status_set,
117+
input [15:0] status_menumask,
86118

87119
input info_req,
88120
input [7:0] info,
@@ -133,31 +165,6 @@ module hps_io #(parameter CONF_STR, CONF_STR_BRAM=1, PS2DIV=0, WIDE=0, VDNUM=1,
133165
output reg [7:0] uart_mode,
134166
output reg [31:0] uart_speed,
135167

136-
// ps2 keyboard emulation
137-
output ps2_kbd_clk_out,
138-
output ps2_kbd_data_out,
139-
input ps2_kbd_clk_in,
140-
input ps2_kbd_data_in,
141-
142-
input [2:0] ps2_kbd_led_status,
143-
input [2:0] ps2_kbd_led_use,
144-
145-
output ps2_mouse_clk_out,
146-
output ps2_mouse_data_out,
147-
input ps2_mouse_clk_in,
148-
input ps2_mouse_data_in,
149-
150-
// ps2 alternative interface.
151-
152-
// [8] - extended, [9] - pressed, [10] - toggles with every press/release
153-
output reg [10:0] ps2_key = 0,
154-
155-
// [24] - toggles with every event
156-
output reg [24:0] ps2_mouse = 0,
157-
output reg [15:0] ps2_mouse_ext = 0, // 15:8 - reserved(additional buttons), 7:0 - wheel movements
158-
159-
inout [21:0] gamma_bus,
160-
161168
// for core-specific extensions
162169
inout [35:0] EXT_BUS
163170
);
@@ -219,14 +226,13 @@ video_calc video_calc
219226
.new_vmode(new_vmode),
220227
.video_rotated(video_rotated),
221228

222-
.par_num(byte_cnt[3:0]),
229+
.par_num(byte_cnt[4:0]),
223230
.dout(vc_dout)
224231
);
225232

226233
/////////////////////////////////////////////////////////
227234

228-
localparam STRLEN = $size(CONF_STR)>>3;
229-
localparam MAX_W = $clog2((32 > (STRLEN+2)) ? 32 : (STRLEN+2))-1;
235+
localparam MAX_W = $clog2((64 > (STRLEN+2)) ? 64 : (STRLEN+2))-1;
230236

231237
wire [7:0] conf_byte;
232238
generate
@@ -259,7 +265,7 @@ always@(posedge clk_sys) begin : uio_block
259265
reg [3:0] pdsp_idx;
260266
reg ps2skip = 0;
261267
reg [3:0] stflg = 0;
262-
reg [63:0] status_req;
268+
reg[127:0] status_req;
263269
reg old_status_set = 0;
264270
reg old_upload_req = 0;
265271
reg upload_req = 0;
@@ -274,7 +280,7 @@ always@(posedge clk_sys) begin : uio_block
274280
stflg <= stflg + 1'd1;
275281
status_req <= status_in;
276282
end
277-
283+
278284
old_upload_req <= ioctl_upload_req;
279285
if(~old_upload_req & ioctl_upload_req) upload_req <= 1;
280286

@@ -330,6 +336,12 @@ always@(posedge clk_sys) begin : uio_block
330336
'h39: io_dout <= 1;
331337
'h3C: if(upload_req) begin io_dout <= {ioctl_upload_index, 8'd1}; upload_req <= 0; end
332338
'h3E: io_dout <= 1; // shadow mask
339+
'h003F: io_dout <= joystick_0_rumble;
340+
'h013F: io_dout <= joystick_1_rumble;
341+
'h023F: io_dout <= joystick_2_rumble;
342+
'h033F: io_dout <= joystick_3_rumble;
343+
'h043F: io_dout <= joystick_4_rumble;
344+
'h053F: io_dout <= joystick_5_rumble;
333345
endcase
334346

335347
sd_buff_addr <= 0;
@@ -455,13 +467,17 @@ always@(posedge clk_sys) begin : uio_block
455467
// send image info
456468
'h1d: if(byte_cnt<5) img_size[{byte_cnt-1'b1, 4'b0000} +:16] <= io_din;
457469

458-
// status, 64bit version
459-
'h1e: if(!byte_cnt[MAX_W:3]) begin
460-
case(byte_cnt[2:0])
461-
1: status[15:00] <= io_din;
462-
2: status[31:16] <= io_din;
463-
3: status[47:32] <= io_din;
464-
4: status[63:48] <= io_din;
470+
// status, 128bit version
471+
'h1e: if(!byte_cnt[MAX_W:4]) begin
472+
case(byte_cnt[3:0])
473+
1: status[15:00] <= io_din;
474+
2: status[31:16] <= io_din;
475+
3: status[47:32] <= io_din;
476+
4: status[63:48] <= io_din;
477+
5: status[79:64] <= io_din;
478+
6: status[95:80] <= io_din;
479+
7: status[111:96] <= io_din;
480+
8: status[127:112] <= io_din;
465481
endcase
466482
end
467483

@@ -485,24 +501,28 @@ always@(posedge clk_sys) begin : uio_block
485501
'h22: RTC[(byte_cnt-6'd1)<<4 +:16] <= io_din;
486502

487503
//Video res.
488-
'h23: if(!byte_cnt[MAX_W:4]) io_dout <= vc_dout;
504+
'h23: if(!byte_cnt[MAX_W:5]) io_dout <= vc_dout;
489505

490506
//RTC
491507
'h24: TIMESTAMP[(byte_cnt-6'd1)<<4 +:16] <= io_din;
492508

493509
//status set
494-
'h29: if(!byte_cnt[MAX_W:3]) begin
495-
case(byte_cnt[2:0])
510+
'h29: if(!byte_cnt[MAX_W:4]) begin
511+
case(byte_cnt[3:0])
496512
1: io_dout <= status_req[15:00];
497513
2: io_dout <= status_req[31:16];
498514
3: io_dout <= status_req[47:32];
499515
4: io_dout <= status_req[63:48];
516+
5: io_dout <= status_req[79:64];
517+
6: io_dout <= status_req[95:80];
518+
7: io_dout <= status_req[111:96];
519+
8: io_dout <= status_req[127:112];
500520
endcase
501521
end
502522

503523
//menu mask
504524
'h2E: if(byte_cnt == 1) io_dout <= status_menumask;
505-
525+
506526
//sdram size set
507527
'h31: if(byte_cnt == 1) sdram_sz <= io_din;
508528

@@ -609,7 +629,7 @@ always@(posedge clk_sys) begin : fio_block
609629
reg has_cmd;
610630
reg [26:0] addr;
611631
reg wr;
612-
632+
613633
ioctl_rd <= 0;
614634
ioctl_wr <= wr;
615635
wr <= 0;
@@ -642,7 +662,7 @@ always@(posedge clk_sys) begin : fio_block
642662
FIO_FILE_TX:
643663
begin
644664
cnt <= cnt + 1'd1;
645-
case(cnt)
665+
case(cnt)
646666
0: if(io_din[7:0] == 8'hAA) begin
647667
ioctl_addr <= 0;
648668
ioctl_upload <= 1;
@@ -851,7 +871,7 @@ module video_calc
851871
input new_vmode,
852872
input video_rotated,
853873

854-
input [3:0] par_num,
874+
input [4:0] par_num,
855875
output reg [15:0] dout
856876
);
857877

@@ -870,29 +890,58 @@ always @(posedge clk_sys) begin
870890
11: dout <= vid_pix[31:16];
871891
12: dout <= vid_vtime_hdmi[15:0];
872892
13: dout <= vid_vtime_hdmi[31:16];
893+
14: dout <= vid_ccnt[15:0];
894+
15: dout <= vid_ccnt[31:16];
895+
16: dout <= vid_pixrep;
896+
17: dout <= vid_de_h;
897+
18: dout <= vid_de_v;
873898
default dout <= 0;
874899
endcase
875900
end
876901

877902
reg [31:0] vid_hcnt = 0;
878903
reg [31:0] vid_vcnt = 0;
904+
reg [31:0] vid_ccnt = 0;
879905
reg [7:0] vid_nres = 0;
880906
reg [1:0] vid_int = 0;
907+
reg [7:0] vid_pixrep;
908+
reg [15:0] vid_de_h;
909+
reg [7:0] vid_de_v;
881910

882911
always @(posedge clk_vid) begin
883912
integer hcnt;
884913
integer vcnt;
885-
reg old_vs= 0, old_de = 0, old_vmode = 0;
914+
integer ccnt;
915+
reg [7:0] pcnt;
916+
reg [7:0] de_v;
917+
reg [15:0] de_h;
918+
reg old_vs = 0, old_hs = 0, old_hs_vclk = 0, old_de = 0, old_de_vclk = 0, old_de1 = 0, old_vmode = 0;
886919
reg [3:0] resto = 0;
887920
reg calch = 0;
888921

922+
if(calch & de) ccnt <= ccnt + 1;
923+
pcnt <= pcnt + 1'd1;
924+
925+
old_hs_vclk <= hs;
926+
de_h <= de_h + 1'd1;
927+
if(old_hs_vclk & ~hs) de_h <= 1;
928+
929+
old_de_vclk <= de;
930+
if(calch & ~old_de_vclk & de) vid_de_h <= de_h;
931+
889932
if(ce_pix) begin
890933
old_vs <= vs;
934+
old_hs <= hs;
891935
old_de <= de;
936+
old_de1 <= old_de;
937+
pcnt <= 1;
892938

893939
if(~vs & ~old_de & de) vcnt <= vcnt + 1;
894940
if(calch & de) hcnt <= hcnt + 1;
895941
if(old_de & ~de) calch <= 0;
942+
if(~old_de1 & old_de) vid_pixrep <= pcnt;
943+
if(old_hs & ~hs) de_v <= de_v + 1'd1;
944+
if(calch & ~old_de & de) vid_de_v <= de_v;
896945

897946
if(old_vs & ~vs) begin
898947
vid_int <= {vid_int[0],f1};
@@ -906,10 +955,13 @@ always @(posedge clk_vid) begin
906955
if(&resto) vid_nres <= vid_nres + 1'd1;
907956
vid_hcnt <= hcnt;
908957
vid_vcnt <= vcnt;
958+
vid_ccnt <= ccnt;
909959
end
910960
vcnt <= 0;
911961
hcnt <= 0;
962+
ccnt <= 0;
912963
calch <= 1;
964+
de_v <= 0;
913965
end
914966
end
915967
end
@@ -979,8 +1031,15 @@ module confstr_rom #(parameter CONF_STR, STRLEN)
9791031
output reg [7:0] conf_byte
9801032
);
9811033

982-
wire [7:0] rom[STRLEN];
983-
initial for(int i = 0; i < STRLEN; i++) rom[i] = CONF_STR[((STRLEN-i)*8)-1 -:8];
1034+
reg [7:0] rom[STRLEN];
1035+
1036+
initial begin
1037+
if( CONF_STR=="" )
1038+
$readmemh("cfgstr.hex",rom);
1039+
else
1040+
for(int i = 0; i < STRLEN; i++) rom[i] = CONF_STR[((STRLEN-i)*8)-1 -:8];
1041+
end
1042+
9841043
always @ (posedge clk_sys) conf_byte <= rom[conf_addr];
9851044

9861045
endmodule

‎sys/i2c.v

+1-1
Original file line numberDiff line numberDiff line change
@@ -75,7 +75,7 @@ always @(posedge CLK) begin
7575
END <= 0;
7676
rd <= READ;
7777
len <= I2C_WLEN;
78-
if(READ) SD <= {2'b10, I2C_ADDR, 1'b1, 1'b1, 8'b11111111, 1'b0, 3'b011, 9'b111111111};
78+
if(READ) SD <= {2'b10, I2C_ADDR, 1'b1, 1'b1, 8'b11111111, 1'b1, 3'b011, 9'b111111111};
7979
else SD <= {2'b10, I2C_ADDR, 1'b0, 1'b1, I2C_WDATA1, 1'b1, I2C_WDATA2, 4'b1011};
8080
SD_COUNTER <= 0;
8181
end else begin

‎sys/ltc2308.sv

+13-13
Original file line numberDiff line numberDiff line change
@@ -102,19 +102,19 @@ end
102102

103103
endmodule
104104

105-
module ltc2308_tape #(parameter HIST_LOW = 16, HIST_HIGH = 64, ADC_RATE = 48000, CLK_RATE = 50000000)
105+
module ltc2308_tape #(parameter HIST_LOW = 16, HIST_HIGH = 64, ADC_RATE = 48000, CLK_RATE = 50000000, NUM_CH = 1)
106106
(
107-
input reset,
108-
input clk,
109-
110-
inout [3:0] ADC_BUS,
111-
output reg dout,
112-
output active
107+
input reset,
108+
input clk,
109+
110+
inout [3:0] ADC_BUS,
111+
output reg dout,
112+
output active,
113+
output adc_sync,
114+
output [(NUM_CH*12)-1:0] adc_data
113115
);
114116

115-
wire [11:0] adc_data;
116-
wire adc_sync;
117-
ltc2308 #(1, ADC_RATE, CLK_RATE) adc
117+
ltc2308 #(NUM_CH, ADC_RATE, CLK_RATE) adc
118118
(
119119
.reset(reset),
120120
.clk(clk),
@@ -133,8 +133,8 @@ always @(posedge clk) begin
133133
data1 <= data2;
134134
data2 <= data3;
135135
data3 <= data4;
136-
data4 <= adc_data;
137-
136+
data4 <= adc_data[11:0];
137+
138138
sum <= data1+data2+data3+data4;
139139

140140
if(sum[13:2]<HIST_LOW) dout <= 0;
@@ -148,7 +148,7 @@ reg [1:0] act;
148148
always @(posedge clk) begin
149149
reg [31:0] onesec;
150150
reg old_dout;
151-
151+
152152
onesec <= onesec + 1;
153153
if(onesec>CLK_RATE) begin
154154
onesec <= 0;

‎sys/mcp23009.sv

+12-5
Original file line numberDiff line numberDiff line change
@@ -8,10 +8,12 @@ module mcp23009
88

99
output reg [2:0] btn,
1010
input [2:0] led,
11-
output reg sd_cd,
11+
output reg flg_sd_cd,
12+
output reg flg_present,
13+
output reg flg_mode,
1214

13-
output scl,
14-
inout sda
15+
output scl,
16+
inout sda
1517
);
1618

1719

@@ -50,7 +52,9 @@ always@(posedge clk) begin
5052
idx <= 0;
5153
btn <= 0;
5254
rw <= 0;
53-
sd_cd <= 1;
55+
flg_sd_cd <= 1;
56+
flg_present <= 0;
57+
flg_mode <= 1;
5458
end
5559
else begin
5660
if(~&init_data[idx]) begin
@@ -84,7 +88,10 @@ always@(posedge clk) begin
8488
state <= 0;
8589
rw <= 0;
8690
if(!error) begin
87-
if(rw) {sd_cd, btn} <= {dout[7], dout[5:3]};
91+
if(rw) begin
92+
{flg_sd_cd, flg_mode, btn} <= {dout[7:3]};
93+
flg_present <= 1;
94+
end
8895
rw <= ~rw;
8996
end
9097
end

‎sys/osd.v

+1-1
Original file line numberDiff line numberDiff line change
@@ -131,7 +131,7 @@ wire [21:0] osd_h_hdr = (info || rot) ? osd_h : (osd_h + OSD_HDR);
131131

132132
// pipeline the comparisons a bit
133133
always @(posedge clk_video) if(ce_pix) begin
134-
v_cnt_h <= v_cnt < osd_t;
134+
v_cnt_h <= v_cnt <= osd_t;
135135
v_cnt_1 <= v_cnt < 320;
136136
v_cnt_2 <= v_cnt < 640;
137137
v_cnt_3 <= v_cnt < 960;

‎sys/pll_cfg.qip

+2-41
Original file line numberDiff line numberDiff line change
@@ -1,44 +1,5 @@
1-
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_NAME "altera_pll_reconfig"
2-
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_VERSION "17.0"
3-
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_ENV "mwpim"
4-
set_global_assignment -library "pll_cfg" -name MISC_FILE [file join $::quartus(qip_path) "pll_cfg.cmp"]
5-
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
6-
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
7-
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_QSYS_MODE "UNKNOWN"
81
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
9-
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_NAME "cGxsX2hkbWlfY2Zn"
10-
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTCBSZWNvbmZpZw=="
11-
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
12-
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_INTERNAL "Off"
13-
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
14-
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_VERSION "MTcuMA=="
15-
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIFJlY29uZmlndXJhdGlvbiBCbG9jayhBTFRFUkFfUExMX1JFQ09ORklHKQ=="
16-
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA=="
17-
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA=="
18-
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA=="
19-
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA=="
20-
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo"
21-
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw=="
22-
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_NAME "YWx0ZXJhX3BsbF9yZWNvbmZpZ190b3A="
23-
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTCBSZWNvbmZpZw=="
24-
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
25-
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_INTERNAL "Off"
26-
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
27-
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_VERSION "MTcuMA=="
28-
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIFJlY29uZmlndXJhdGlvbiBCbG9jayhBTFRFUkFfUExMX1JFQ09ORklHKQ=="
29-
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "ZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBW::ZGV2aWNlX2ZhbWlseQ=="
30-
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01JRg==::ZmFsc2U=::RW5hYmxlIE1JRiBTdHJlYW1pbmc="
31-
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA=="
32-
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA=="
33-
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA=="
34-
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA=="
35-
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo"
36-
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw=="
37-
38-
set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg.v"]
2+
set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/pll_cfg.v"]
3+
set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/pll_cfg_hdmi.v"]
394
set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/altera_pll_reconfig_top.v"]
405
set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/altera_pll_reconfig_core.v"]
41-
42-
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_NAME "altera_pll_reconfig"
43-
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_VERSION "17.0"
44-
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_ENV "mwpim"

‎sys/pll_cfg/altera_pll_reconfig_core.v

+3-3
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616
module altera_pll_reconfig_core
1717
#(
1818
parameter reconf_width = 64,
19-
parameter device_family = "Stratix V",
19+
parameter device_family = "Cyclone V",
2020
// MIF Streaming parameters
2121
parameter RECONFIG_ADDR_WIDTH = 6,
2222
parameter RECONFIG_DATA_WIDTH = 32,
@@ -1883,7 +1883,7 @@ module fpll_dprio_init (
18831883
endmodule
18841884
module dyn_phase_shift
18851885
#(
1886-
parameter device_family = "Stratix V"
1886+
parameter device_family = "Cyclone V"
18871887
) (
18881888

18891889
input wire clk,
@@ -2112,7 +2112,7 @@ endmodule
21122112
module generic_lcell_comb
21132113
#(
21142114
//parameter
2115-
parameter family = "Stratix V",
2115+
parameter family = "Cyclone V",
21162116
parameter lut_mask = 64'hAAAAAAAAAAAAAAAA,
21172117
parameter dont_touch = "on"
21182118
) (

‎sys/pll_cfg/altera_pll_reconfig_top.v

+1-1
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616
module altera_pll_reconfig_top
1717
#(
1818
parameter reconf_width = 64,
19-
parameter device_family = "Stratix V",
19+
parameter device_family = "Cyclone V",
2020
parameter RECONFIG_ADDR_WIDTH = 6,
2121
parameter RECONFIG_DATA_WIDTH = 32,
2222

‎sys/pll_cfg.v ‎sys/pll_cfg/pll_cfg.v

+86-86
Original file line numberDiff line numberDiff line change
@@ -1,86 +1,86 @@
1-
// megafunction wizard: %Altera PLL Reconfig v17.0%
2-
// GENERATION: XML
3-
// pll_cfg.v
4-
5-
// Generated using ACDS version 17.0 598
6-
7-
`timescale 1 ps / 1 ps
8-
module pll_cfg #(
9-
parameter ENABLE_BYTEENABLE = 0,
10-
parameter BYTEENABLE_WIDTH = 4,
11-
parameter RECONFIG_ADDR_WIDTH = 6,
12-
parameter RECONFIG_DATA_WIDTH = 32,
13-
parameter reconf_width = 64,
14-
parameter WAIT_FOR_LOCK = 1
15-
) (
16-
input wire mgmt_clk, // mgmt_clk.clk
17-
input wire mgmt_reset, // mgmt_reset.reset
18-
output wire mgmt_waitrequest, // mgmt_avalon_slave.waitrequest
19-
input wire mgmt_read, // .read
20-
input wire mgmt_write, // .write
21-
output wire [31:0] mgmt_readdata, // .readdata
22-
input wire [5:0] mgmt_address, // .address
23-
input wire [31:0] mgmt_writedata, // .writedata
24-
output wire [63:0] reconfig_to_pll, // reconfig_to_pll.reconfig_to_pll
25-
input wire [63:0] reconfig_from_pll // reconfig_from_pll.reconfig_from_pll
26-
);
27-
28-
altera_pll_reconfig_top #(
29-
.device_family ("Cyclone V"),
30-
.ENABLE_MIF (0),
31-
.MIF_FILE_NAME ("sys/pll_cfg.mif"),
32-
.ENABLE_BYTEENABLE (ENABLE_BYTEENABLE),
33-
.BYTEENABLE_WIDTH (BYTEENABLE_WIDTH),
34-
.RECONFIG_ADDR_WIDTH (RECONFIG_ADDR_WIDTH),
35-
.RECONFIG_DATA_WIDTH (RECONFIG_DATA_WIDTH),
36-
.reconf_width (reconf_width),
37-
.WAIT_FOR_LOCK (WAIT_FOR_LOCK)
38-
) pll_cfg_inst (
39-
.mgmt_clk (mgmt_clk), // mgmt_clk.clk
40-
.mgmt_reset (mgmt_reset), // mgmt_reset.reset
41-
.mgmt_waitrequest (mgmt_waitrequest), // mgmt_avalon_slave.waitrequest
42-
.mgmt_read (mgmt_read), // .read
43-
.mgmt_write (mgmt_write), // .write
44-
.mgmt_readdata (mgmt_readdata), // .readdata
45-
.mgmt_address (mgmt_address), // .address
46-
.mgmt_writedata (mgmt_writedata), // .writedata
47-
.reconfig_to_pll (reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll
48-
.reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll
49-
.mgmt_byteenable (4'b0000) // (terminated)
50-
);
51-
52-
endmodule
53-
// Retrieval info: <?xml version="1.0"?>
54-
//<!--
55-
// Generated by Altera MegaWizard Launcher Utility version 1.0
56-
// ************************************************************
57-
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
58-
// ************************************************************
59-
// Copyright (C) 1991-2018 Altera Corporation
60-
// Any megafunction design, and related net list (encrypted or decrypted),
61-
// support information, device programming or simulation file, and any other
62-
// associated documentation or information provided by Altera or a partner
63-
// under Altera's Megafunction Partnership Program may be used only to
64-
// program PLD devices (but not masked PLD devices) from Altera. Any other
65-
// use of such megafunction design, net list, support information, device
66-
// programming or simulation file, or any other related documentation or
67-
// information is prohibited for any other purpose, including, but not
68-
// limited to modification, reverse engineering, de-compiling, or use with
69-
// any other silicon devices, unless such use is explicitly licensed under
70-
// a separate agreement with Altera or a megafunction partner. Title to
71-
// the intellectual property, including patents, copyrights, trademarks,
72-
// trade secrets, or maskworks, embodied in any such megafunction design,
73-
// net list, support information, device programming or simulation file, or
74-
// any other related documentation or information provided by Altera or a
75-
// megafunction partner, remains with Altera, the megafunction partner, or
76-
// their respective licensors. No other licenses, including any licenses
77-
// needed under any third party's intellectual property, are provided herein.
78-
//-->
79-
// Retrieval info: <instance entity-name="altera_pll_reconfig" version="17.0" >
80-
// Retrieval info: <generic name="device_family" value="Cyclone V" />
81-
// Retrieval info: <generic name="ENABLE_MIF" value="false" />
82-
// Retrieval info: <generic name="MIF_FILE_NAME" value="sys/pll_cfg.mif" />
83-
// Retrieval info: <generic name="ENABLE_BYTEENABLE" value="false" />
84-
// Retrieval info: </instance>
85-
// IPFS_FILES : pll_cfg.vo
86-
// RELATED_FILES: pll_cfg.v, altera_pll_reconfig_top.v, altera_pll_reconfig_core.v, altera_std_synchronizer.v
1+
// megafunction wizard: %Altera PLL Reconfig v17.0%
2+
// GENERATION: XML
3+
// pll_cfg.v
4+
5+
// Generated using ACDS version 17.0 598
6+
7+
`timescale 1 ps / 1 ps
8+
module pll_cfg #(
9+
parameter ENABLE_BYTEENABLE = 0,
10+
parameter BYTEENABLE_WIDTH = 4,
11+
parameter RECONFIG_ADDR_WIDTH = 6,
12+
parameter RECONFIG_DATA_WIDTH = 32,
13+
parameter reconf_width = 64,
14+
parameter WAIT_FOR_LOCK = 1
15+
) (
16+
input wire mgmt_clk, // mgmt_clk.clk
17+
input wire mgmt_reset, // mgmt_reset.reset
18+
output wire mgmt_waitrequest, // mgmt_avalon_slave.waitrequest
19+
input wire mgmt_read, // .read
20+
input wire mgmt_write, // .write
21+
output wire [31:0] mgmt_readdata, // .readdata
22+
input wire [5:0] mgmt_address, // .address
23+
input wire [31:0] mgmt_writedata, // .writedata
24+
output wire [63:0] reconfig_to_pll, // reconfig_to_pll.reconfig_to_pll
25+
input wire [63:0] reconfig_from_pll // reconfig_from_pll.reconfig_from_pll
26+
);
27+
28+
altera_pll_reconfig_top #(
29+
.device_family ("Cyclone V"),
30+
.ENABLE_MIF (0),
31+
.MIF_FILE_NAME ("sys/pll_cfg.mif"),
32+
.ENABLE_BYTEENABLE (ENABLE_BYTEENABLE),
33+
.BYTEENABLE_WIDTH (BYTEENABLE_WIDTH),
34+
.RECONFIG_ADDR_WIDTH (RECONFIG_ADDR_WIDTH),
35+
.RECONFIG_DATA_WIDTH (RECONFIG_DATA_WIDTH),
36+
.reconf_width (reconf_width),
37+
.WAIT_FOR_LOCK (WAIT_FOR_LOCK)
38+
) pll_cfg_inst (
39+
.mgmt_clk (mgmt_clk), // mgmt_clk.clk
40+
.mgmt_reset (mgmt_reset), // mgmt_reset.reset
41+
.mgmt_waitrequest (mgmt_waitrequest), // mgmt_avalon_slave.waitrequest
42+
.mgmt_read (mgmt_read), // .read
43+
.mgmt_write (mgmt_write), // .write
44+
.mgmt_readdata (mgmt_readdata), // .readdata
45+
.mgmt_address (mgmt_address), // .address
46+
.mgmt_writedata (mgmt_writedata), // .writedata
47+
.reconfig_to_pll (reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll
48+
.reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll
49+
.mgmt_byteenable (4'b0000) // (terminated)
50+
);
51+
52+
endmodule
53+
// Retrieval info: <?xml version="1.0"?>
54+
//<!--
55+
// Generated by Altera MegaWizard Launcher Utility version 1.0
56+
// ************************************************************
57+
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
58+
// ************************************************************
59+
// Copyright (C) 1991-2018 Altera Corporation
60+
// Any megafunction design, and related net list (encrypted or decrypted),
61+
// support information, device programming or simulation file, and any other
62+
// associated documentation or information provided by Altera or a partner
63+
// under Altera's Megafunction Partnership Program may be used only to
64+
// program PLD devices (but not masked PLD devices) from Altera. Any other
65+
// use of such megafunction design, net list, support information, device
66+
// programming or simulation file, or any other related documentation or
67+
// information is prohibited for any other purpose, including, but not
68+
// limited to modification, reverse engineering, de-compiling, or use with
69+
// any other silicon devices, unless such use is explicitly licensed under
70+
// a separate agreement with Altera or a megafunction partner. Title to
71+
// the intellectual property, including patents, copyrights, trademarks,
72+
// trade secrets, or maskworks, embodied in any such megafunction design,
73+
// net list, support information, device programming or simulation file, or
74+
// any other related documentation or information provided by Altera or a
75+
// megafunction partner, remains with Altera, the megafunction partner, or
76+
// their respective licensors. No other licenses, including any licenses
77+
// needed under any third party's intellectual property, are provided herein.
78+
//-->
79+
// Retrieval info: <instance entity-name="altera_pll_reconfig" version="17.0" >
80+
// Retrieval info: <generic name="device_family" value="Cyclone V" />
81+
// Retrieval info: <generic name="ENABLE_MIF" value="false" />
82+
// Retrieval info: <generic name="MIF_FILE_NAME" value="sys/pll_cfg.mif" />
83+
// Retrieval info: <generic name="ENABLE_BYTEENABLE" value="false" />
84+
// Retrieval info: </instance>
85+
// IPFS_FILES : pll_cfg.vo
86+
// RELATED_FILES: pll_cfg.v, altera_pll_reconfig_top.v, altera_pll_reconfig_core.v, altera_std_synchronizer.v

‎sys/pll_cfg/pll_cfg_hdmi.v

+1,282
Large diffs are not rendered by default.

‎sys/pll_q13.qip

+1-3
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,4 @@
11
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.13.qip ]
22
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.13.qip ]
33
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.13.qip ]
4-
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg.v ]
5-
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_core.v ]
6-
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_top.v ]
4+
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ]

‎sys/sys.qip

+1-1
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) v
1616
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) arcade_video.v ]
1717
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) osd.v ]
1818
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) vga_out.sv ]
19+
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) yc_out.sv ]
1920
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2c.v ]
2021
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) alsa.sv ]
2122
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2s.v ]
@@ -25,7 +26,6 @@ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i
2526
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ltc2308.sv ]
2627
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sigma_delta_dac.v ]
2728
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) mt32pi.sv ]
28-
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hdmi_config.sv ]
2929
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) mcp23009.sv ]
3030
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) f2sdram_safe_terminator.sv ]
3131
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr_svc.sv ]

‎sys/sys.tcl

-7
Original file line numberDiff line numberDiff line change
@@ -16,13 +16,6 @@ set_location_assignment PIN_V10 -to ADC_SCK
1616
set_location_assignment PIN_AC4 -to ADC_SDI
1717
set_location_assignment PIN_AD4 -to ADC_SDO
1818

19-
#============================================================
20-
# ARDUINO
21-
#============================================================
22-
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[*]
23-
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[*]
24-
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ARDUINO_IO[*]
25-
2619
#============================================================
2720
# I2C LEDS/BUTTONS
2821
#============================================================

‎sys/sys_dual_sdram.tcl

+1
Original file line numberDiff line numberDiff line change
@@ -45,6 +45,7 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM2_
4545
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM2_*
4646
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM2_DQ[*]
4747
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM2_DQ[*]
48+
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDRAM2_DQ[*]
4849
set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM2_*
4950

5051
set_global_assignment -name VERILOG_MACRO "MISTER_DUAL_SDRAM=1"

‎sys/sys_top.sdc

+9-3
Original file line numberDiff line numberDiff line change
@@ -25,14 +25,17 @@ set_false_path -from [get_ports {KEY*}]
2525
set_false_path -from [get_ports {BTN_*}]
2626
set_false_path -to [get_ports {LED_*}]
2727
set_false_path -to [get_ports {VGA_*}]
28+
set_false_path -from [get_ports {VGA_EN}]
2829
set_false_path -to [get_ports {AUDIO_SPDIF}]
2930
set_false_path -to [get_ports {AUDIO_L}]
3031
set_false_path -to [get_ports {AUDIO_R}]
32+
set_false_path -from {get_ports {SW[*]}}
3133
set_false_path -to {cfg[*]}
3234
set_false_path -from {cfg[*]}
3335
set_false_path -from {VSET[*]}
3436
set_false_path -to {wcalc[*] hcalc[*]}
35-
set_false_path -to {hdmi_width[*] hdmi_height[*]}
37+
set_false_path -to {hdmi_width[*] hdmi_height[*]}
38+
set_false_path -to {deb_* btn_en btn_up}
3639

3740
set_multicycle_path -to {*_osd|osd_vcnt*} -setup 2
3841
set_multicycle_path -to {*_osd|osd_vcnt*} -hold 1
@@ -55,17 +58,20 @@ set_false_path -from {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] LFB_HMIN[*]
5558
set_false_path -to {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]}
5659
set_false_path -from {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]}
5760
set_false_path -from {aflt_* acx* acy* areset* arc*}
61+
set_false_path -from {arx* ary*}
5862
set_false_path -from {vs_line*}
63+
set_false_path -from {ColorBurst_Range* PhaseInc* pal_en cvbs yc_en}
5964

6065
set_false_path -from {ascal|o_ihsize*}
6166
set_false_path -from {ascal|o_ivsize*}
6267
set_false_path -from {ascal|o_format*}
6368
set_false_path -from {ascal|o_hdown}
6469
set_false_path -from {ascal|o_vdown}
65-
set_false_path -from {ascal|o_hmin* ascal|o_hmax* ascal|o_vmin* ascal|o_vmax*}
70+
set_false_path -from {ascal|o_hmin* ascal|o_hmax* ascal|o_vmin* ascal|o_vmax* ascal|o_vrrmax* ascal|o_vrr}
6671
set_false_path -from {ascal|o_hdisp* ascal|o_vdisp*}
6772
set_false_path -from {ascal|o_htotal* ascal|o_vtotal*}
6873
set_false_path -from {ascal|o_hsstart* ascal|o_vsstart* ascal|o_hsend* ascal|o_vsend*}
6974
set_false_path -from {ascal|o_hsize* ascal|o_vsize*}
7075

71-
set_false_path -from {mcp23009|sd_cd}
76+
set_false_path -from {mcp23009|flg_*}
77+
set_false_path -to {sysmem|fpga_interfaces|clocks_resets*}

‎sys/sys_top.v

+616-440
Large diffs are not rendered by default.

‎sys/vga_out.sv

+26-21
Original file line numberDiff line numberDiff line change
@@ -7,23 +7,27 @@ module vga_out
77
input hsync,
88
input vsync,
99
input csync,
10+
input de,
1011

1112
input [23:0] din,
1213
output [23:0] dout,
1314

1415
output reg hsync_o,
1516
output reg vsync_o,
16-
output reg csync_o
17+
output reg csync_o,
18+
output reg de_o
1719
);
1820

19-
wire [5:0] red = din[23:18];
20-
wire [5:0] green = din[15:10];
21-
wire [5:0] blue = din[7:2];
21+
wire [7:0] red = din[23:16];
22+
wire [7:0] green = din[15:8];
23+
wire [7:0] blue = din[7:0];
2224

2325
// http://marsee101.blog19.fc2.com/blog-entry-2311.html
24-
// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B)
25-
// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
26-
// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B)
26+
27+
28+
// Y = 0.301*R + 0.586*G + 0.113*B (Y = 0.299*R + 0.587*G + 0.114*B)
29+
// Pb = 128 - 0.168*R - 0.332*G + 0.500*B (Pb = -0.169*R - 0.331*G + 0.500*B)
30+
// Pr = 128 + 0.500*R - 0.418*G - 0.082*B (Pr = 0.500*R - 0.419*G - 0.081*B)
2731

2832
reg [7:0] y, pb, pr;
2933
reg [23:0] rgb;
@@ -33,32 +37,33 @@ always @(posedge clk) begin
3337
reg [18:0] y_1b, pb_1b, pr_1b;
3438
reg [18:0] y_2, pb_2, pr_2;
3539
reg [23:0] din1, din2;
36-
reg hsync2, vsync2, csync2;
37-
reg hsync1, vsync1, csync1;
40+
reg hsync2, vsync2, csync2, de2;
41+
reg hsync1, vsync1, csync1, de1;
3842

39-
y_1r <= 19'd04096 + ({red, 8'd0} + {red, 3'd0});
40-
pb_1r <= 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0});
41-
pr_1r <= 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0});
43+
y_1r <= {red, 6'd0} + {red, 3'd0} + {red, 2'd0} + red;
44+
pb_1r <= 19'd32768 - ({red, 5'd0} + {red, 3'd0} + {red, 1'd0});
45+
pr_1r <= 19'd32768 + {red, 7'd0};
4246

43-
y_1g <= {green, 9'd0} + {green, 2'd0};
44-
pb_1g <= {green, 8'd0} + {green, 5'd0} + {green, 3'd0};
45-
pr_1g <= {green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0};
47+
y_1g <= {green, 7'd0} + {green, 4'd0} + {green, 2'd0} + {green, 1'd0};
48+
pb_1g <= {green, 6'd0} + {green, 4'd0} + {green, 2'd0} + green;
49+
pr_1g <= {green, 6'd0} + {green, 5'd0} + {green, 3'd0} + {green, 1'd0};
4650

47-
y_1b <= {blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0};
48-
pb_1b <= {blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0};
49-
pr_1b <= {blue, 6'd0} + {blue, 3'd0};
51+
y_1b <= {blue, 4'd0} + {blue, 3'd0} + {blue, 2'd0} + blue;
52+
pb_1b <= {blue, 7'd0};
53+
pr_1b <= {blue, 4'd0} + {blue, 2'd0} + blue;
5054

5155
y_2 <= y_1r + y_1g + y_1b;
5256
pb_2 <= pb_1r - pb_1g + pb_1b;
5357
pr_2 <= pr_1r - pr_1g - pr_1b;
5458

55-
y <= ( y_2[18] || !y_2[17:12]) ? 8'd16 : (y_2[17:8] > 235) ? 8'd235 : y_2[15:8];
56-
pb <= (pb_2[18] || !pb_2[17:12]) ? 8'd16 : (&pb_2[17:12]) ? 8'd240 : pb_2[15:8];
57-
pr <= (pr_2[18] || !pr_2[17:12]) ? 8'd16 : (&pr_2[17:12]) ? 8'd240 : pr_2[15:8];
59+
y <= y_2[18] ? 8'd0 : y_2[16] ? 8'd255 : y_2[15:8];
60+
pb <= pb_2[18] ? 8'd0 : pb_2[16] ? 8'd255 : pb_2[15:8];
61+
pr <= pr_2[18] ? 8'd0 : pr_2[16] ? 8'd255 : pr_2[15:8];
5862

5963
hsync_o <= hsync2; hsync2 <= hsync1; hsync1 <= hsync;
6064
vsync_o <= vsync2; vsync2 <= vsync1; vsync1 <= vsync;
6165
csync_o <= csync2; csync2 <= csync1; csync1 <= csync;
66+
de_o <= de2; de2 <= de1; de1 <= de;
6267

6368
rgb <= din2; din2 <= din1; din1 <= din;
6469
end

‎sys/video_cleaner.sv

+11-2
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,10 @@ module video_cleaner
2626
//optional de
2727
input DE_in,
2828

29+
//optional interlace support
30+
input interlace,
31+
input f1,
32+
2933
// video output signals
3034
output reg [7:0] VGA_R,
3135
output reg [7:0] VGA_G,
@@ -56,14 +60,19 @@ always @(posedge clk_vid) begin
5660
HBlank_out <= hbl;
5761

5862
VGA_HS <= hs;
59-
if(~VGA_HS & hs) VGA_VS <= vs;
6063

6164
VGA_R <= R;
6265
VGA_G <= G;
6366
VGA_B <= B;
6467
DE_out <= DE_in;
6568

66-
if(HBlank_out & ~hbl) VBlank_out <= vbl;
69+
if (interlace & f1) begin
70+
VGA_VS <= vs;
71+
VBlank_out <= vbl;
72+
end else begin
73+
if(~VGA_HS & hs) VGA_VS <= vs;
74+
if(HBlank_out & ~hbl) VBlank_out <= vbl;
75+
end
6776
end
6877
end
6978

‎sys/video_freak.sv

+64-13
Original file line numberDiff line numberDiff line change
@@ -170,10 +170,8 @@ reg [11:0] mul_arg1, mul_arg2;
170170
wire [23:0] mul_res;
171171
sys_umul #(12,12) mul(CLK_VIDEO,mul_start,mul_run, mul_arg1,mul_arg2,mul_res);
172172

173-
wire [11:0] wideres = mul_res[11:0] + hsize;
174-
175173
always @(posedge CLK_VIDEO) begin
176-
reg [11:0] oheight,wres;
174+
reg [11:0] oheight,htarget,wres,hinteger,wideres;
177175
reg [12:0] arxf,aryf;
178176
reg [3:0] cnt;
179177
reg narrow;
@@ -188,11 +186,18 @@ always @(posedge CLK_VIDEO) begin
188186
else if(~div_start & ~div_run & ~mul_start & ~mul_run) begin
189187
cnt <= cnt + 1'd1;
190188
case(cnt)
189+
// example ideal and non-ideal cases:
190+
// [1] 720x400 4:3 VGA 80x25 text-mode (non-square pixels)
191+
// [2] 640x480 4:3 VGA graphics mode (square pixels)
192+
// [3] 512x512 4:3 X68000 graphics mode (non-square pixels)
191193
0: begin
192194
div_num <= HDMI_HEIGHT;
193195
div_den <= vsize;
194196
div_start <= 1;
195197
end
198+
// [1] 1080 / 400 -> 2
199+
// [2] 1080 / 480 -> 2
200+
// [3] 1080 / 512 -> 2
196201

197202
1: if(!div_res[11:0]) begin
198203
// screen resolution is lower than video resolution.
@@ -206,6 +211,9 @@ always @(posedge CLK_VIDEO) begin
206211
mul_arg2 <= div_res[11:0];
207212
mul_start <= 1;
208213
end
214+
// [1] 1080 / 400 * 400 -> 800
215+
// [2] 1080 / 480 * 480 -> 960
216+
// [3] 1080 / 512 * 512 -> 1024
209217

210218
2: begin
211219
oheight <= mul_res[11:0];
@@ -219,51 +227,94 @@ always @(posedge CLK_VIDEO) begin
219227
mul_arg2 <= arx_i;
220228
mul_start <= 1;
221229
end
230+
// [1] 1080 / 400 * 400 * 4 -> 3200
231+
// [2] 1080 / 480 * 480 * 4 -> 3840
232+
// [3] 1080 / 512 * 512 * 4 -> 4096
222233

223234
4: begin
224235
div_num <= mul_res;
225236
div_den <= ary_i;
226237
div_start <= 1;
227238
end
239+
// [1] 1080 / 480 * 480 * 4 / 3 -> 1066
240+
// [2] 1080 / 480 * 480 * 4 / 3 -> 1280
241+
// [3] 1080 / 512 * 512 * 4 / 3 -> 1365
242+
// saved as htarget
228243

229244
5: begin
245+
htarget <= div_res[11:0];
230246
div_num <= div_res;
231247
div_den <= hsize;
232248
div_start <= 1;
233249
end
250+
// computes wide scaling factor as a ceiling division
251+
// [1] 1080 / 400 * 400 * 4 / 3 / 720 -> 1
252+
// [2] 1080 / 480 * 480 * 4 / 3 / 640 -> 2
253+
// [3] 1080 / 512 * 512 * 4 / 3 / 512 -> 2
234254

235255
6: begin
236256
mul_arg1 <= hsize;
237257
mul_arg2 <= div_res[11:0] ? div_res[11:0] : 12'd1;
238258
mul_start <= 1;
239259
end
260+
// [1] 1080 / 400 * 400 * 4 / 3 / 720 * 720 -> 720
261+
// [2] 1080 / 480 * 480 * 4 / 3 / 640 * 640 -> 1280
262+
// [3] 1080 / 512 * 512 * 4 / 3 / 512 * 512 -> 1024
240263

241264
7: if(mul_res <= HDMI_WIDTH) begin
242-
cnt <= 10;
265+
hinteger = mul_res[11:0];
266+
cnt <= 12;
243267
end
244268

245269
8: begin
246270
div_num <= HDMI_WIDTH;
247271
div_den <= hsize;
248272
div_start <= 1;
249273
end
274+
// [1] 1920 / 720 -> 2
275+
// [2] 1920 / 640 -> 3
276+
// [3] 1920 / 512 -> 3
250277

251278
9: begin
252279
mul_arg1 <= hsize;
253280
mul_arg2 <= div_res[11:0] ? div_res[11:0] : 12'd1;
254281
mul_start <= 1;
255282
end
256-
257-
10: begin
258-
narrow <= ((div_num[11:0] - mul_res[11:0]) <= (wideres - div_num[11:0])) || (wideres > HDMI_WIDTH);
259-
wres <= wideres;
283+
// [1] 1920 / 720 * 720 -> 1440
284+
// [2] 1920 / 640 * 640 -> 1920
285+
// [3] 1920 / 512 * 512 -> 1536
286+
287+
10: begin
288+
hinteger <= mul_res[11:0];
289+
mul_arg1 <= vsize;
290+
mul_arg2 <= div_res[11:0] ? div_res[11:0] : 12'd1;
291+
mul_start <= 1;
292+
end
293+
294+
11: begin
295+
oheight <= mul_res[11:0];
296+
end
297+
298+
12: begin
299+
wideres <= hinteger + hsize;
300+
narrow <= ((htarget - hinteger) <= (wideres - htarget)) || (wideres > HDMI_WIDTH);
301+
wres <= hinteger == htarget ? hinteger : wideres;
260302
end
261-
262-
11: begin
303+
// [1] 1066 - 720 = 346 <= 1440 - 1066 = 374 || 1440 > 1920 -> true
304+
// [2] 1280 - 1280 = 0 <= 1920 - 1280 = 640 || 1920 > 1920 -> true
305+
// [3] 1365 - 1024 = 341 <= 1536 - 1365 = 171 || 1536 > 1920 -> false
306+
// 1. narrow flag is true when mul_res[11:0] narrow width is closer to
307+
// htarget aspect ratio target width or when wideres wider width
308+
// does not fit to the screen.
309+
// 2. wres becomes wideres only when mul_res[11:0] narrow width not equal
310+
// to target width, meaning it is not optimal for source aspect ratio.
311+
// otherwise it is set to narrow width that is optimal.
312+
313+
13: begin
263314
case(SCALE)
264-
2: arxf <= {1'b1, mul_res[11:0]};
265-
3: arxf <= {1'b1, (wres > HDMI_WIDTH) ? mul_res[11:0] : wres};
266-
4: arxf <= {1'b1, narrow ? mul_res[11:0] : wres};
315+
2: arxf <= {1'b1, hinteger};
316+
3: arxf <= {1'b1, (wres > HDMI_WIDTH) ? hinteger : wres};
317+
4: arxf <= {1'b1, narrow ? hinteger : wres};
267318
default: arxf <= {1'b1, div_num[11:0]};
268319
endcase
269320
aryf <= {1'b1, oheight};

‎sys/yc_out.sv

+233
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,233 @@
1+
//============================================================================
2+
// YC - Luma / Chroma Generation
3+
// Copyright (C) 2022 Mike Simone
4+
//
5+
// This program is free software; you can redistribute it and/or modify it
6+
// under the terms of the GNU General Public License as published by the Free
7+
// Software Foundation; either version 2 of the License, or (at your option)
8+
// any later version.
9+
//
10+
// This program is distributed in the hope that it will be useful, but WITHOUT
11+
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12+
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13+
// more details.
14+
//
15+
// You should have received a copy of the GNU General Public License along
16+
// with this program; if not, write to the Free Software Foundation, Inc.,
17+
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
18+
//
19+
//============================================================================
20+
/*
21+
Colorspace
22+
Y 0.299R' + 0.587G' + 0.114B'
23+
U 0.492(B' - Y) = 504 (X 1024)
24+
V 0.877(R' - Y) = 898 (X 1024)
25+
*/
26+
//////////////////////////////////////////////////////////
27+
28+
module yc_out
29+
(
30+
input clk,
31+
input [39:0] PHASE_INC,
32+
input PAL_EN,
33+
input CVBS,
34+
input [16:0] COLORBURST_RANGE,
35+
36+
input hsync,
37+
input vsync,
38+
input csync,
39+
input de,
40+
41+
input [23:0] din,
42+
output [23:0] dout,
43+
44+
output reg hsync_o,
45+
output reg vsync_o,
46+
output reg csync_o,
47+
output reg de_o
48+
);
49+
50+
wire [7:0] red = din[23:16];
51+
wire [7:0] green = din[15:8];
52+
wire [7:0] blue = din[7:0];
53+
54+
logic [9:0] red_1, blue_1, green_1, red_2, blue_2, green_2;
55+
56+
logic signed [20:0] yr = 0, yb = 0, yg = 0;
57+
58+
typedef struct {
59+
logic signed [20:0] y;
60+
logic signed [20:0] c;
61+
logic signed [20:0] u;
62+
logic signed [20:0] v;
63+
logic hsync;
64+
logic vsync;
65+
logic csync;
66+
logic de;
67+
} phase_t;
68+
69+
localparam MAX_PHASES = 7'd8;
70+
71+
phase_t phase[MAX_PHASES];
72+
reg unsigned [7:0] Y, C, c, U, V;
73+
74+
75+
reg [10:0] cburst_phase; // colorburst counter
76+
reg unsigned [7:0] vref = 'd128; // Voltage reference point (Used for Chroma)
77+
logic [7:0] chroma_LUT_COS; // Chroma cos LUT reference
78+
logic [7:0] chroma_LUT_SIN; // Chroma sin LUT reference
79+
logic [7:0] chroma_LUT_BURST; // Chroma colorburst LUT reference
80+
logic [7:0] chroma_LUT = 8'd0;
81+
82+
/*
83+
THe following LUT table was calculated by Sin(2*pi*t/2^8) where t: 0 - 255
84+
*/
85+
86+
/*************************************
87+
8 bit Sine look up Table
88+
**************************************/
89+
wire signed [10:0] chroma_SIN_LUT[256] = '{
90+
11'h000, 11'h006, 11'h00C, 11'h012, 11'h018, 11'h01F, 11'h025, 11'h02B, 11'h031, 11'h037, 11'h03D, 11'h044, 11'h04A, 11'h04F,
91+
11'h055, 11'h05B, 11'h061, 11'h067, 11'h06D, 11'h072, 11'h078, 11'h07D, 11'h083, 11'h088, 11'h08D, 11'h092, 11'h097, 11'h09C,
92+
11'h0A1, 11'h0A6, 11'h0AB, 11'h0AF, 11'h0B4, 11'h0B8, 11'h0BC, 11'h0C1, 11'h0C5, 11'h0C9, 11'h0CC, 11'h0D0, 11'h0D4, 11'h0D7,
93+
11'h0DA, 11'h0DD, 11'h0E0, 11'h0E3, 11'h0E6, 11'h0E9, 11'h0EB, 11'h0ED, 11'h0F0, 11'h0F2, 11'h0F4, 11'h0F5, 11'h0F7, 11'h0F8,
94+
11'h0FA, 11'h0FB, 11'h0FC, 11'h0FD, 11'h0FD, 11'h0FE, 11'h0FE, 11'h0FE, 11'h0FF, 11'h0FE, 11'h0FE, 11'h0FE, 11'h0FD, 11'h0FD,
95+
11'h0FC, 11'h0FB, 11'h0FA, 11'h0F8, 11'h0F7, 11'h0F5, 11'h0F4, 11'h0F2, 11'h0F0, 11'h0ED, 11'h0EB, 11'h0E9, 11'h0E6, 11'h0E3,
96+
11'h0E0, 11'h0DD, 11'h0DA, 11'h0D7, 11'h0D4, 11'h0D0, 11'h0CC, 11'h0C9, 11'h0C5, 11'h0C1, 11'h0BC, 11'h0B8, 11'h0B4, 11'h0AF,
97+
11'h0AB, 11'h0A6, 11'h0A1, 11'h09C, 11'h097, 11'h092, 11'h08D, 11'h088, 11'h083, 11'h07D, 11'h078, 11'h072, 11'h06D, 11'h067,
98+
11'h061, 11'h05B, 11'h055, 11'h04F, 11'h04A, 11'h044, 11'h03D, 11'h037, 11'h031, 11'h02B, 11'h025, 11'h01F, 11'h018, 11'h012,
99+
11'h00C, 11'h006, 11'h000, 11'h7F9, 11'h7F3, 11'h7ED, 11'h7E7, 11'h7E0, 11'h7DA, 11'h7D4, 11'h7CE, 11'h7C8, 11'h7C2, 11'h7BB,
100+
11'h7B5, 11'h7B0, 11'h7AA, 11'h7A4, 11'h79E, 11'h798, 11'h792, 11'h78D, 11'h787, 11'h782, 11'h77C, 11'h777, 11'h772, 11'h76D,
101+
11'h768, 11'h763, 11'h75E, 11'h759, 11'h754, 11'h750, 11'h74B, 11'h747, 11'h743, 11'h73E, 11'h73A, 11'h736, 11'h733, 11'h72F,
102+
11'h72B, 11'h728, 11'h725, 11'h722, 11'h71F, 11'h71C, 11'h719, 11'h716, 11'h714, 11'h712, 11'h70F, 11'h70D, 11'h70B, 11'h70A,
103+
11'h708, 11'h707, 11'h705, 11'h704, 11'h703, 11'h702, 11'h702, 11'h701, 11'h701, 11'h701, 11'h701, 11'h701, 11'h701, 11'h701,
104+
11'h702, 11'h702, 11'h703, 11'h704, 11'h705, 11'h707, 11'h708, 11'h70A, 11'h70B, 11'h70D, 11'h70F, 11'h712, 11'h714, 11'h716,
105+
11'h719, 11'h71C, 11'h71F, 11'h722, 11'h725, 11'h728, 11'h72B, 11'h72F, 11'h733, 11'h736, 11'h73A, 11'h73E, 11'h743, 11'h747,
106+
11'h74B, 11'h750, 11'h754, 11'h759, 11'h75E, 11'h763, 11'h768, 11'h76D, 11'h772, 11'h777, 11'h77C, 11'h782, 11'h787, 11'h78D,
107+
11'h792, 11'h798, 11'h79E, 11'h7A4, 11'h7AA, 11'h7B0, 11'h7B5, 11'h7BB, 11'h7C2, 11'h7C8, 11'h7CE, 11'h7D4, 11'h7DA, 11'h7E0,
108+
11'h7E7, 11'h7ED, 11'h7F3, 11'h7F9
109+
};
110+
111+
logic [39:0] phase_accum;
112+
logic PAL_FLIP = 1'd0;
113+
logic PAL_line_count = 1'd0;
114+
115+
/**************************************
116+
Generate Luma and Chroma Signals
117+
***************************************/
118+
119+
always_ff @(posedge clk) begin
120+
for (logic [3:0] x = 0; x < (MAX_PHASES - 1'd1); x = x + 1'd1) begin
121+
phase[x + 1] <= phase[x];
122+
end
123+
124+
// delay red / blue signals to align luma with U/V calculation (Fixes colorbleeding)
125+
red_1 <= red;
126+
blue_1 <= blue;
127+
red_2 <= red_1;
128+
blue_2 <= blue_1;
129+
130+
// Calculate Luma signal
131+
yr <= {red, 8'd0} + {red, 5'd0}+ {red, 4'd0} + {red, 1'd0};
132+
yg <= {green, 9'd0} + {green, 6'd0} + {green, 4'd0} + {green, 3'd0} + green;
133+
yb <= {blue, 6'd0} + {blue, 5'd0} + {blue, 4'd0} + {blue, 2'd0} + blue;
134+
phase[0].y <= yr + yg + yb;
135+
136+
// Generate the LUT values using the phase accumulator reference.
137+
phase_accum <= phase_accum + PHASE_INC;
138+
chroma_LUT <= phase_accum[39:32];
139+
140+
// Adjust SINE carrier reference for PAL (Also adjust for PAL Switch)
141+
if (PAL_EN) begin
142+
if (PAL_FLIP)
143+
chroma_LUT_BURST <= chroma_LUT + 8'd160;
144+
else
145+
chroma_LUT_BURST <= chroma_LUT + 8'd96;
146+
end else // Adjust SINE carrier reference for NTSC
147+
chroma_LUT_BURST <= chroma_LUT + 8'd128;
148+
149+
// Prepare LUT values for sin / cos (+90 degress)
150+
chroma_LUT_SIN <= chroma_LUT;
151+
chroma_LUT_COS <= chroma_LUT + 8'd64;
152+
153+
// Calculate for U, V - Bit Shift Multiple by u = by * 1024 x 0.492 = 504, v = ry * 1024 x 0.877 = 898
154+
phase[0].u <= $signed({2'b0 ,(blue_2)}) - $signed({2'b0 ,phase[0].y[17:10]});
155+
phase[0].v <= $signed({2'b0 , (red_2)}) - $signed({2'b0 ,phase[0].y[17:10]});
156+
phase[1].u <= 21'($signed({phase[0].u, 8'd0}) + $signed({phase[0].u, 7'd0}) + $signed({phase[0].u, 6'd0}) + $signed({phase[0].u, 5'd0}) + $signed({phase[0].u, 4'd0}) + $signed({phase[0].u, 3'd0}));
157+
phase[1].v <= 21'($signed({phase[0].v, 9'd0}) + $signed({phase[0].v, 8'd0}) + $signed({phase[0].v, 7'd0}) + $signed({phase[0].v, 1'd0}));
158+
159+
phase[0].c <= vref;
160+
phase[1].c <= phase[0].c;
161+
phase[2].c <= phase[1].c;
162+
phase[3].c <= phase[2].c;
163+
164+
if (hsync) begin // Reset colorburst counter, as well as the calculated cos / sin values.
165+
cburst_phase <= 'd0;
166+
phase[2].u <= 21'b0;
167+
phase[2].v <= 21'b0;
168+
phase[4].c <= phase[3].c;
169+
170+
if (PAL_line_count) begin
171+
PAL_FLIP <= ~PAL_FLIP;
172+
PAL_line_count <= ~PAL_line_count;
173+
end
174+
end
175+
else begin // Generate Colorburst for 9 cycles
176+
if (cburst_phase >= COLORBURST_RANGE[16:10] && cburst_phase <= COLORBURST_RANGE[9:0]) begin // Start the color burst signal at 40 samples or 0.9 us
177+
// COLORBURST SIGNAL GENERATION (9 CYCLES ONLY or between count 40 - 240)
178+
phase[2].u <= $signed({chroma_SIN_LUT[chroma_LUT_BURST],5'd0});
179+
phase[2].v <= 21'b0;
180+
181+
// Division to scale down the results to fit 8 bit.
182+
if (PAL_EN)
183+
phase[3].u <= $signed(phase[2].u[20:8]) + $signed(phase[2].u[20:10]) + $signed(phase[2].u[20:14]);
184+
else
185+
phase[3].u <= $signed(phase[2].u[20:8]) + $signed(phase[2].u[20:11]) + $signed(phase[2].u[20:12]) + $signed(phase[2].u[20:13]);
186+
187+
phase[3].v <= phase[2].v;
188+
end else begin // MODULATE U, V for chroma
189+
/*
190+
U,V are both multiplied by 1024 earlier to scale for the decimals in the YUV colorspace conversion.
191+
U and V are both divided by 2^10 which introduce chroma subsampling of 4:1:1 (25% or from 8 bit to 6 bit)
192+
*/
193+
phase[2].u <= $signed((phase[1].u)>>>10) * $signed(chroma_SIN_LUT[chroma_LUT_SIN]);
194+
phase[2].v <= $signed((phase[1].v)>>>10) * $signed(chroma_SIN_LUT[chroma_LUT_COS]);
195+
196+
// Divide U*sin(wt) and V*cos(wt) to fit results to 8 bit
197+
phase[3].u <= $signed(phase[2].u[20:9]) + $signed(phase[2].u[20:10]) + $signed(phase[2].u[20:14]);
198+
phase[3].v <= $signed(phase[2].v[20:9]) + $signed(phase[2].v[20:10]) + $signed(phase[2].u[20:14]);
199+
end
200+
201+
// Stop the colorburst timer as its only needed for the initial pulse
202+
if (cburst_phase <= COLORBURST_RANGE[9:0])
203+
cburst_phase <= cburst_phase + 9'd1;
204+
205+
// Calculate for chroma (Note: "PAL SWITCH" routine flips V * COS(Wt) every other line)
206+
if (PAL_EN) begin
207+
if (PAL_FLIP)
208+
phase[4].c <= vref + phase[3].u - phase[3].v;
209+
else
210+
phase[4].c <= vref + phase[3].u + phase[3].v;
211+
PAL_line_count <= 1'd1;
212+
end else
213+
phase[4].c <= vref + phase[3].u + phase[3].v;
214+
end
215+
216+
// Adjust sync timing correctly
217+
phase[1].hsync <= hsync; phase[1].vsync <= vsync; phase[1].csync <= csync; phase[1].de <= de;
218+
phase[2].hsync <= phase[1].hsync; phase[2].vsync <= phase[1].vsync; phase[2].csync <= phase[1].csync; phase[2].de <= phase[1].de;
219+
phase[3].hsync <= phase[2].hsync; phase[3].vsync <= phase[2].vsync; phase[3].csync <= phase[2].csync; phase[3].de <= phase[2].de;
220+
phase[4].hsync <= phase[3].hsync; phase[4].vsync <= phase[3].vsync; phase[4].csync <= phase[3].csync; phase[4].de <= phase[3].de;
221+
hsync_o <= phase[4].hsync; vsync_o <= phase[4].vsync; csync_o <= phase[4].csync; de_o <= phase[4].de;
222+
223+
phase[1].y <= phase[0].y; phase[2].y <= phase[1].y; phase[3].y <= phase[2].y; phase[4].y <= phase[3].y; phase[5].y <= phase[4].y;
224+
225+
// Set Chroma / Luma output
226+
C <= CVBS ? 8'd0 : phase[4].c[7:0];
227+
Y <= CVBS ? ({1'b0, phase[5].y[17:11]} + {1'b0, phase[4].c[7:1]}) : phase[5].y[17:10];
228+
end
229+
230+
assign dout = {C, Y, 8'd0};
231+
232+
endmodule
233+

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