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Corey Whartonandrewboie
Corey Wharton
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kconfig: Make the CPU_HAS_FPU_DOUBLE_PRECISION option global.
This option now applies to the RISC-V architecture and is no longer a ARM only configuration. Signed-off-by: Corey Wharton <[email protected]>
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10 files changed

+25
-31
lines changed

10 files changed

+25
-31
lines changed

arch/Kconfig

+7-7
Original file line numberDiff line numberDiff line change
@@ -464,6 +464,13 @@ config CPU_HAS_FPU
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This option is enabled when the CPU has hardware floating point
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unit.
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467+
config CPU_HAS_FPU_DOUBLE_PRECISION
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bool
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select CPU_HAS_FPU
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help
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When enabled, this indicates that the CPU has a double floating point
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precision unit.
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config CPU_HAS_MPU
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bool
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help
@@ -531,13 +538,6 @@ config FP_SHARING
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This option allows multiple threads to use the floating point
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registers.
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534-
config FLOAT_64BIT
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bool "Double precision floating point"
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depends on FLOAT
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depends on RISCV
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help
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This option means that floating point registers are 64bit width.
540-
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config ARCH
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string
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help

cmake/compiler/gcc/target_riscv.cmake

+11-9
Original file line numberDiff line numberDiff line change
@@ -12,16 +12,18 @@ else()
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string(CONCAT riscv_march ${riscv_march} "32ima")
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endif()
1414

15-
if(CONFIG_FLOAT_64BIT)
16-
if(CONFIG_FLOAT_HARD)
17-
string(CONCAT riscv_mabi ${riscv_mabi} "d")
15+
if(CONFIG_FLOAT)
16+
if(CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION)
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if(CONFIG_FLOAT_HARD)
18+
string(CONCAT riscv_mabi ${riscv_mabi} "d")
19+
endif()
20+
string(CONCAT riscv_march ${riscv_march} "fd")
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else()
22+
if(CONFIG_FLOAT_HARD)
23+
string(CONCAT riscv_mabi ${riscv_mabi} "f")
24+
endif()
25+
string(CONCAT riscv_march ${riscv_march} "f")
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endif()
19-
string(CONCAT riscv_march ${riscv_march} "fd")
20-
elseif(CONFIG_FLOAT)
21-
if(CONFIG_FLOAT_HARD)
22-
string(CONCAT riscv_mabi ${riscv_mabi} "f")
23-
endif()
24-
string(CONCAT riscv_march ${riscv_march} "f")
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endif()
2628

2729
if(CONFIG_COMPRESSED_ISA)

include/arch/riscv/arch.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,7 @@
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#define RV_REGSHIFT 2
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#endif
4242

43-
#ifdef CONFIG_FLOAT_64BIT
43+
#ifdef CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION
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#define RV_OP_LOADFPREG fld
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#define RV_OP_STOREFPREG fsd
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#else

include/arch/riscv/exp.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@ struct soc_esf {
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#endif
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4444
#if !defined(RV_FP_TYPE) && defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING)
45-
#ifdef CONFIG_FLOAT_64BIT
45+
#ifdef CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION
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#define RV_FP_TYPE u64_t
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#else
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#define RV_FP_TYPE u32_t

include/arch/riscv/thread.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@
2323
#include <zephyr/types.h>
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2525
#if !defined(RV_FP_TYPE) && defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING)
26-
#ifdef CONFIG_FLOAT_64BIT
26+
#ifdef CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION
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#define RV_FP_TYPE u64_t
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#else
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#define RV_FP_TYPE u32_t

soc/arm/Kconfig

-8
Original file line numberDiff line numberDiff line change
@@ -57,14 +57,6 @@ config NRF_SPU_RAM_REGION_SIZE
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RAM region size for the NRF_SPU peripheral
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endif
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60-
config CPU_HAS_FPU_DOUBLE_PRECISION
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bool
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depends on CPU_CORTEX_M7
63-
select CPU_HAS_FPU
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help
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When enabled, indicates that the SoC has a double
66-
floating point precision unit.
67-
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config HAS_SWO
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bool
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help

tests/kernel/fp_sharing/float_disable/src/k_float_disable.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,7 @@ void test_k_float_disable_common(void)
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"usr_fp_thread FP options not set (0x%0x)",
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usr_fp_thread.base.user_options);
8080

81-
#if defined(CONFIG_ARM) || defined(RISCV)
81+
#if defined(CONFIG_ARM) || defined(CONFIG_RISCV)
8282
/* Verify FP mode can only be disabled for current thread */
8383
zassert_true((k_float_disable(&usr_fp_thread) == -EINVAL),
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"k_float_disable() successful on thread other than current!");

tests/kernel/fp_sharing/generic/src/float_context.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -109,7 +109,7 @@ struct fp_non_volatile_register_set {
109109
#elif defined(CONFIG_RISCV)
110110

111111
struct fp_volatile_register_set {
112-
#ifdef CONFIG_FLOAT_64BIT
112+
#ifdef CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION
113113
u64_t fp[32];
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#else
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u32_t fp[32];

tests/kernel/fp_sharing/generic/src/float_regs_riscv_gcc.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@
1919
#include <toolchain.h>
2020
#include "float_context.h"
2121

22-
#ifdef CONFIG_FLOAT_64BIT
22+
#ifdef CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION
2323
#define RV_FPREG_WIDTH 8
2424
#define RV_FPREG_SAVE "fsd "
2525
#define RV_FPREG_LOAD "fld "

tests/kernel/fp_sharing/generic/src/test_common.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
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/*
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* Test Thread Parameters
1111
*/
12-
#define THREAD_STACK_SIZE 2048
12+
#define THREAD_STACK_SIZE 1024
1313

1414
#define THREAD_HIGH_PRIORITY 5
1515
#define THREAD_LOW_PRIORITY 10

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