From b2b4cbe5442ccaef9c5c631a6f5f35f8c528c462 Mon Sep 17 00:00:00 2001 From: Ksenia Dobrovolskaya Date: Thu, 13 Feb 2025 15:18:54 +0000 Subject: [PATCH] [snippy] Illegal instruction during initialization by splats Removed optimization of the number of mode change instructions to fix the bug. --- .../llvm-snippy/lib/Target/RISCV/RVVUnitConfig.h | 12 ------------ .../tools/llvm-snippy/lib/Target/RISCV/Target.cpp | 15 ++------------- .../lib/Target/RISCV/TargetGenContext.h | 9 --------- 3 files changed, 2 insertions(+), 34 deletions(-) diff --git a/llvm/tools/llvm-snippy/lib/Target/RISCV/RVVUnitConfig.h b/llvm/tools/llvm-snippy/lib/Target/RISCV/RVVUnitConfig.h index db8a1f9d2440..286b4be2ff5c 100644 --- a/llvm/tools/llvm-snippy/lib/Target/RISCV/RVVUnitConfig.h +++ b/llvm/tools/llvm-snippy/lib/Target/RISCV/RVVUnitConfig.h @@ -105,13 +105,6 @@ struct RVVConfiguration final { void print(raw_ostream &OS) const; void dump() const; - - bool operator==(const RVVConfiguration &Other) const { - return LMUL == Other.LMUL && SEW == Other.SEW && - MaskAgnostic == Other.MaskAgnostic && - TailAgnostic == Other.TailAgnostic && VXRM == Other.VXRM && - VxsatEnable == Other.VxsatEnable; - } }; inline static bool isLegalSEW(unsigned SEW) { @@ -217,11 +210,6 @@ struct RVVConfigurationInfo final { struct VLVM { unsigned VL; APInt VM; - - bool operator==(const VLVM &Other) const { - return VL == Other.VL && VM.getBitWidth() == Other.VM.getBitWidth() && - VM == Other.VM; - } }; static RVVConfigurationInfo diff --git a/llvm/tools/llvm-snippy/lib/Target/RISCV/Target.cpp b/llvm/tools/llvm-snippy/lib/Target/RISCV/Target.cpp index c60b97671a05..0dfd0f57200b 100644 --- a/llvm/tools/llvm-snippy/lib/Target/RISCV/Target.cpp +++ b/llvm/tools/llvm-snippy/lib/Target/RISCV/Target.cpp @@ -1270,13 +1270,7 @@ class SnippyRISCVTarget final : public SnippyTarget { auto [RVVConfig, VLVM] = constructRVVModeWithVMReset(RISCVII::VLMUL::LMUL_1, VLen, SEW, TA, MA); const RVVModeInfo NewRVVMode{VLVM, RVVConfig, MBB}; - - const auto &RGC = - ProgCtx.getTargetContext().getImpl(); - - if (!RGC.hasActiveRVVMode(MBB) || RGC.getActiveRVVMode(MBB) != NewRVVMode) { - generateRVVModeUpdate(IGC, InstrInfo, NewRVVMode); - } + generateRVVModeUpdate(IGC, InstrInfo, NewRVVMode); // Initialize registers before taking a branch // V0 is the mask register, skip it. @@ -3322,12 +3316,7 @@ void SnippyRISCVTarget::rvvUnsafeWriteValueUsingXReg( auto [RVVConfig, VLVM] = constructRVVModeWithVMReset(RISCVII::VLMUL::LMUL_1, VL, SEW, TA, MA); const RVVModeInfo NewRVVMode{VLVM, RVVConfig, MBB}; - const auto &RGC = ProgCtx.getTargetContext().getImpl(); - - // We might already have needed RVVMode - if (!RGC.hasActiveRVVMode(MBB) || RGC.getActiveRVVMode(MBB) != NewRVVMode) { - generateRVVModeUpdate(IGC, InstrInfo, NewRVVMode); - } + generateRVVModeUpdate(IGC, InstrInfo, NewRVVMode); // Use non-reserved reg as scratch. auto &RI = State.getRegInfo(); diff --git a/llvm/tools/llvm-snippy/lib/Target/RISCV/TargetGenContext.h b/llvm/tools/llvm-snippy/lib/Target/RISCV/TargetGenContext.h index 025e3598ec86..ac940e0f81e9 100644 --- a/llvm/tools/llvm-snippy/lib/Target/RISCV/TargetGenContext.h +++ b/llvm/tools/llvm-snippy/lib/Target/RISCV/TargetGenContext.h @@ -30,15 +30,6 @@ struct RVVModeInfo { RVVModeInfo(RVVConfigurationInfo::VLVM RVV_VLVM, const RVVConfiguration &RVVCfg, const MachineBasicBlock &MBB) : VLVM{std::move(RVV_VLVM)}, Config{&RVVCfg}, MBBGuard{&MBB} {} - - bool operator==(const RVVModeInfo &Other) const { - return VLVM == Other.VLVM && MBBGuard == Other.MBBGuard && - ((Config != nullptr && Other.Config != nullptr && - *Config == *Other.Config) || - (Config == nullptr && Other.Config == nullptr)); - } - - bool operator!=(const RVVModeInfo &Other) const { return !(*this == Other); } }; struct VSETWeightOverrides {