qm32.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity qm32 is
	generic (
			constant DATA_WIDTH: integer:= 32
	);
	port 
	(
		A	: in std_logic_vector(DATA_WIDTH-1 downto 0);
		B	: in std_logic_vector(DATA_WIDTH-1 downto 0);
		V	: out std_logic_vector(DATA_WIDTH*2-1 downto 0)
	);
end entity;

architecture qm32 of qm32 is
type mux_results_type	is array (DATA_WIDTH/2-1 downto 0) of std_logic_vector(DATA_WIDTH+1 downto 0);
type tmp_array is array(DATA_WIDTH/2-1 downto 0) of std_logic_vector(DATA_WIDTH*2-1 downto 0);
signal s3A: std_logic_vector(DATA_WIDTH+1 downto 0);
signal r:	mux_results_type;
signal tmp: tmp_array;

component my_mux
	generic (
			DATA_WIDTH: integer:= 32
	);
	port
	(
		dataA	: in STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0);
		data3A	: in STD_LOGIC_VECTOR (DATA_WIDTH+1 DOWNTO 0);
		sel		: in STD_LOGIC_VECTOR (1 DOWNTO 0);
		result	: out STD_LOGIC_VECTOR (DATA_WIDTH+1 DOWNTO 0)
	);
end component;

component parallel_add0
	PORT
	(
		data0x		: IN STD_LOGIC_VECTOR (33 DOWNTO 0);
		data10x		: IN STD_LOGIC_VECTOR (33 DOWNTO 0);
		data11x		: IN STD_LOGIC_VECTOR (33 DOWNTO 0);
		data12x		: IN STD_LOGIC_VECTOR (33 DOWNTO 0);
		data13x		: IN STD_LOGIC_VECTOR (33 DOWNTO 0);
		data14x		: IN STD_LOGIC_VECTOR (33 DOWNTO 0);
		data15x		: IN STD_LOGIC_VECTOR (33 DOWNTO 0);
		data1x		: IN STD_LOGIC_VECTOR (33 DOWNTO 0);
		data2x		: IN STD_LOGIC_VECTOR (33 DOWNTO 0);
		data3x		: IN STD_LOGIC_VECTOR (33 DOWNTO 0);
		data4x		: IN STD_LOGIC_VECTOR (33 DOWNTO 0);
		data5x		: IN STD_LOGIC_VECTOR (33 DOWNTO 0);
		data6x		: IN STD_LOGIC_VECTOR (33 DOWNTO 0);
		data7x		: IN STD_LOGIC_VECTOR (33 DOWNTO 0);
		data8x		: IN STD_LOGIC_VECTOR (33 DOWNTO 0);
		data9x		: IN STD_LOGIC_VECTOR (33 DOWNTO 0);
		result		: OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
	);
END component;

begin
	s3A <= ("00"&A) + (A&"0");
	gen_mux:
		for i in 0 to DATA_WIDTH/2-1 generate
			muxI: my_mux generic map (DATA_WIDTH => DATA_WIDTH)
				port map (
				A,
				s3A,
				B(i+i+1 downto i+i),
				r(i));
	end generate gen_mux;
-----------------------------
--      for 32bit data     --
-----------------------------
--	V <= r(0)+(r(1)&"00")+(r(2)&"0000")+(r(3)&"000000")+(r(4)&"00000000")+(r(5)&"0000000000")+(r(6)&"000000000000")+(r(7)&"00000000000000")+(r(8)&"0000000000000000")+(r(9)&"000000000000000000")+(r(10)&"00000000000000000000")+(r(11)&"0000000000000000000000")+(r(12)&"000000000000000000000000")+(r(13)&"00000000000000000000000000")+(r(14)&"0000000000000000000000000000")+("0"&r(15)&"000000000000000000000000000000");
-----------------------------
--      for other data     --
-----------------------------
	gen_sum:
		for i in 0 to DATA_WIDTH/2-1 generate
		sum0:
			if i=0 generate
				tmp(i) <= ((DATA_WIDTH-3 downto 0 => '0')&r(i))+(r(i+1)&((i+1)*2-1 downto 0 => '0'));
			end generate;
		sumI:
			if i>0 and i<DATA_WIDTH/2-1 generate
				tmp(i) <= tmp(i-1)+(r(i+1)&((i+1)*2-1 downto 0 => '0'));
			end generate;
		sumN:
			if i=DATA_WIDTH/2-1 generate
				V <= (tmp(i-1))+(r(i)&(DATA_WIDTH-3 downto 0 => '0'));
			end generate;
	end generate gen_sum;
--padder: parallel_add0 port map
--(
--	data0x=>r(0),
--	data1x=>r(1),
--	data2x=>r(2),
--	data3x=>r(3),
--	data4x=>r(4),
--	data5x=>r(5),
--	data6x=>r(6),
--	data7x=>r(7),
--	data8x=>r(8),
--	data9x=>r(9),
--	data10x=>r(10),
--	data11x=>r(11),
--	data12x=>r(12),
--	data13x=>r(13),
--	data14x=>r(14),
--	data15x=>r(15),
--	result=>V
--);
end;