-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathQuickMultiply.qsf
63 lines (58 loc) · 3.3 KB
/
QuickMultiply.qsf
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
# Copyright (C) 1991-2008 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
# The default values for assignments are stored in the file
# QuickMultiply_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
# assignment_defaults.qdf
# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C35F672C6
set_global_assignment -name TOP_LEVEL_ENTITY qm32
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:06:53 JANUARY 16, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION 8.1
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name QIP_FILE lpm_mux0.qip
set_global_assignment -name BDF_FILE scheme.bdf
set_global_assignment -name QIP_FILE lpm_add_sub0.qip
set_global_assignment -name QIP_FILE lpm_add_sub1.qip
set_global_assignment -name VHDL_FILE QuickMultiply.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE test.vwf
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name END_TIME "100 ns"
set_global_assignment -name QIP_FILE lpm_mult0.qip
set_global_assignment -name BDF_FILE sch1.bdf
set_global_assignment -name MISC_FILE "d:/Proj/diploma/QuickMultiply/QuickMultiply.dpf"
set_global_assignment -name VHDL_FILE my_mux.vhd
set_global_assignment -name VHDL_FILE shortQM.vhd
set_global_assignment -name VHDL_FILE qm32.vhd
set_global_assignment -name QIP_FILE lpm_mux1.qip
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name QIP_FILE lpm_mult1.qip
set_global_assignment -name VECTOR_WAVEFORM_FILE multLib32test.vwf
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE test.vwf
set_global_assignment -name QIP_FILE parallel_add0.qip
set_global_assignment -name AHDL_FILE my_amux.tdf
set_global_assignment -name AHDL_FILE aqm.tdf