Consider changing the default timescale #8
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gabrielrutsch
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Apr 27, 2020
…_ctrl to devel/1_3_4 * commit 'fe6c74b3f7ab4cb8c3678c0be8df5da0bd303484': (41 commits) Small adaptations for PS Pilot INICIO_DEV-2029 FIXED execute FPGA link to result root directory Revert "ADDED risetime in preserve function to avoid that our sqaure wave is interpolated in a wrong way." ADDED support in waveform conversion to also record signal changes that are not linked to a time event properly ADDED a flag to indicate whether or not a signal shall be associated to the original cycle count, or emu time fix broken master branch v0.2.0 prepare for release try running sim/emu test through pytest fix missing requirement fix broken tests FIXED minor issue occurring after merge regarding msdsl changes on features that were newly added to anasymod and features from interactive sim ctrl that were not tested extensively before. UPDATED all existing testcases to be compliant to msdsl and svreal changes UPDATED anasymod interactive sim ctrl testcase from Steven to work with latest anasymod changes -> FPGA simulation case updated but not tested yet!! REMOVED hard wired path to vivado bin folder and make use of generic vivado path query feature. FIXED float_type instance attribute treatment in Analysis class. Previously, it was not initialized properly in case that msdsl plugin was not used. FIXED adding libraries for VHDL sources FIXED conversion from multi bit digital signals to integer ADDED Tobi's fix for displaying stdout when running external tools properly UPDATED documentation ADDED initial API for interactive FPGA sim control ADDED interactive testcase for filter example, is passing NOTE regression test will be added within Inicio 2.0 regression, until then the test needs to be started manually due to incompatibility of wexpect and any python IDE -> building the regression test is a little more cumbersome Fix build badge v0.1.9 try to fix buildkite try to fix buildkite ...
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It looks like the default timescale (for Icarus at least) is
1s/1s. This can lead to some unusual results due to very low time resolution (e.g., a failure in thefunctiontest when trying to wait until a bit after a clock edge). I suggest we change to a default with higher resolution; two that I have commonly used are:1ns/1ps(digital design)1s/1ps(analog modeling)Unfortunately this implementation of this feature would be simulator dependent. For example, with Icarus Verilog one needs to create a command file and then add a default timescale command (described here)
Thoughts on what a good default timescale would be and whether this would cause any issues?
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