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Minor fixes
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‎11_virtual_memory/README.md

+25-21
Original file line numberDiff line numberDiff line change
@@ -87,25 +87,29 @@ is hardcoded here (`64 KiB` page descriptors).
8787
The actual page tables are stored in a global instance of the `PageTables` struct:
8888

8989
```rust
90-
// Two newtypes for added type safety, so that you cannot accidentally place a TableDescriptor into
91-
// a PageDescriptor slot in `struct PageTables`, and vice versa.
90+
/// A table descriptor for 64 KiB aperture.
91+
///
92+
/// The output points to the next table.
9293
#[derive(Copy, Clone)]
9394
#[repr(transparent)]
94-
struct RawTableDescriptor(u64);
95+
struct TableDescriptor(u64);
9596

97+
/// A page descriptor with 64 KiB aperture.
98+
///
99+
/// The output points to physical memory.
96100
#[derive(Copy, Clone)]
97101
#[repr(transparent)]
98-
struct RawPageDescriptor(u64);
102+
struct PageDescriptor(u64);
99103

100104
/// Big monolithic struct for storing the page tables. Individual levels must be 64 KiB aligned,
101105
/// hence the "reverse" order of appearance.
102106
#[repr(C)]
103107
#[repr(align(65536))]
104108
struct PageTables<const N: usize> {
105109
// Page descriptors, covering 64 KiB windows per entry.
106-
lvl3: [[RawPageDescriptor; 8192]; N],
110+
lvl3: [[PageDescriptor; 8192]; N],
107111
// Table descriptors, covering 512 MiB windows.
108-
lvl2: [RawTableDescriptor; N],
112+
lvl2: [TableDescriptor; N],
109113
}
110114

111115
/// Usually evaluates to 1 GiB for RPi3 and 4 GiB for RPi 4.
@@ -115,8 +119,8 @@ const ENTRIES_512_MIB: usize = bsp::addr_space_size() >> FIVETWELVE_MIB_SHIFT;
115119
///
116120
/// Supposed to land in `.bss`. Therefore, ensure that they boil down to all "0" entries.
117121
static mut TABLES: PageTables<{ ENTRIES_512_MIB }> = PageTables {
118-
lvl3: [[RawPageDescriptor(0); 8192]; ENTRIES_512_MIB],
119-
lvl2: [RawTableDescriptor(0); ENTRIES_512_MIB],
122+
lvl3: [[PageDescriptor(0); 8192]; ENTRIES_512_MIB],
123+
lvl2: [TableDescriptor(0); ENTRIES_512_MIB],
120124
};
121125
```
122126

@@ -135,11 +139,11 @@ memory and device memory (which is not cached).
135139
fn set_up_mair() {
136140
// Define the memory types being mapped.
137141
MAIR_EL1.write(
138-
// Attribute 1 - Cacheable normal DRAM
142+
// Attribute 1 - Cacheable normal DRAM.
139143
MAIR_EL1::Attr1_HIGH::Memory_OuterWriteBack_NonTransient_ReadAlloc_WriteAlloc
140144
+ MAIR_EL1::Attr1_LOW_MEMORY::InnerWriteBack_NonTransient_ReadAlloc_WriteAlloc
141145

142-
// Attribute 0 - Device
146+
// Attribute 0 - Device.
143147
+ MAIR_EL1::Attr0_HIGH::Device
144148
+ MAIR_EL1::Attr0_LOW_DEVICE::Device_nGnRE,
145149
);
@@ -303,7 +307,7 @@ diff -uNr 10_privilege_level/src/arch/aarch64/mmu.rs 11_virtual_memory/src/arch/
303307
+// A level 3 page descriptor, as per AArch64 Reference Manual Figure D4-17.
304308
+register_bitfields! {u64,
305309
+ STAGE1_PAGE_DESCRIPTOR [
306-
+ /// Privileged execute-never
310+
+ /// Privileged execute-never.
307311
+ PXN OFFSET(53) NUMBITS(1) [
308312
+ False = 0,
309313
+ True = 1
@@ -312,27 +316,27 @@ diff -uNr 10_privilege_level/src/arch/aarch64/mmu.rs 11_virtual_memory/src/arch/
312316
+ /// Physical address of the next page table (lvl2) or the page descriptor (lvl3).
313317
+ OUTPUT_ADDR_64KiB OFFSET(16) NUMBITS(32) [], // [47:16]
314318
+
315-
+ /// Access flag
319+
+ /// Access flag.
316320
+ AF OFFSET(10) NUMBITS(1) [
317321
+ False = 0,
318322
+ True = 1
319323
+ ],
320324
+
321-
+ /// Shareability field
325+
+ /// Shareability field.
322326
+ SH OFFSET(8) NUMBITS(2) [
323327
+ OuterShareable = 0b10,
324328
+ InnerShareable = 0b11
325329
+ ],
326330
+
327-
+ /// Access Permissions
331+
+ /// Access Permissions.
328332
+ AP OFFSET(6) NUMBITS(2) [
329333
+ RW_EL1 = 0b00,
330334
+ RW_EL1_EL0 = 0b01,
331335
+ RO_EL1 = 0b10,
332336
+ RO_EL1_EL0 = 0b11
333337
+ ],
334338
+
335-
+ /// Memory attributes index into the MAIR_EL1 register
339+
+ /// Memory attributes index into the MAIR_EL1 register.
336340
+ AttrIndx OFFSET(2) NUMBITS(3) [],
337341
+
338342
+ TYPE OFFSET(1) NUMBITS(1) [
@@ -418,7 +422,7 @@ diff -uNr 10_privilege_level/src/arch/aarch64/mmu.rs 11_virtual_memory/src/arch/
418422
+ for register::FieldValue<u64, STAGE1_PAGE_DESCRIPTOR::Register>
419423
+{
420424
+ fn from(attribute_fields: AttributeFields) -> Self {
421-
+ // Memory attributes
425+
+ // Memory attributes.
422426
+ let mut desc = match attribute_fields.mem_attributes {
423427
+ MemAttributes::CacheableDRAM => {
424428
+ STAGE1_PAGE_DESCRIPTOR::SH::InnerShareable
@@ -430,13 +434,13 @@ diff -uNr 10_privilege_level/src/arch/aarch64/mmu.rs 11_virtual_memory/src/arch/
430434
+ }
431435
+ };
432436
+
433-
+ // Access Permissions
437+
+ // Access Permissions.
434438
+ desc += match attribute_fields.acc_perms {
435439
+ AccessPermissions::ReadOnly => STAGE1_PAGE_DESCRIPTOR::AP::RO_EL1,
436440
+ AccessPermissions::ReadWrite => STAGE1_PAGE_DESCRIPTOR::AP::RW_EL1,
437441
+ };
438442
+
439-
+ // Execute Never
443+
+ // Execute Never.
440444
+ desc += if attribute_fields.execute_never {
441445
+ STAGE1_PAGE_DESCRIPTOR::PXN::True
442446
+ } else {
@@ -472,11 +476,11 @@ diff -uNr 10_privilege_level/src/arch/aarch64/mmu.rs 11_virtual_memory/src/arch/
472476
+fn set_up_mair() {
473477
+ // Define the memory types being mapped.
474478
+ MAIR_EL1.write(
475-
+ // Attribute 1 - Cacheable normal DRAM
479+
+ // Attribute 1 - Cacheable normal DRAM.
476480
+ MAIR_EL1::Attr1_HIGH::Memory_OuterWriteBack_NonTransient_ReadAlloc_WriteAlloc
477481
+ + MAIR_EL1::Attr1_LOW_MEMORY::InnerWriteBack_NonTransient_ReadAlloc_WriteAlloc
478482
+
479-
+ // Attribute 0 - Device
483+
+ // Attribute 0 - Device.
480484
+ + MAIR_EL1::Attr0_HIGH::Device
481485
+ + MAIR_EL1::Attr0_LOW_DEVICE::Device_nGnRE,
482486
+ );
@@ -560,7 +564,7 @@ diff -uNr 10_privilege_level/src/arch/aarch64/mmu.rs 11_virtual_memory/src/arch/
560564
+ // Enable the MMU and turn on data and instruction caching.
561565
+ SCTLR_EL1.modify(SCTLR_EL1::M::Enable + SCTLR_EL1::C::Cacheable + SCTLR_EL1::I::Cacheable);
562566
+
563-
+ // Force MMU init to complete before next instruction
567+
+ // Force MMU init to complete before next instruction.
564568
+ barrier::isb(barrier::SY);
565569
+
566570
+ Ok(())

‎11_virtual_memory/src/arch/aarch64/mmu.rs

+11-11
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@ register_bitfields! {u64,
3535
// A level 3 page descriptor, as per AArch64 Reference Manual Figure D4-17.
3636
register_bitfields! {u64,
3737
STAGE1_PAGE_DESCRIPTOR [
38-
/// Privileged execute-never
38+
/// Privileged execute-never.
3939
PXN OFFSET(53) NUMBITS(1) [
4040
False = 0,
4141
True = 1
@@ -44,27 +44,27 @@ register_bitfields! {u64,
4444
/// Physical address of the next page table (lvl2) or the page descriptor (lvl3).
4545
OUTPUT_ADDR_64KiB OFFSET(16) NUMBITS(32) [], // [47:16]
4646

47-
/// Access flag
47+
/// Access flag.
4848
AF OFFSET(10) NUMBITS(1) [
4949
False = 0,
5050
True = 1
5151
],
5252

53-
/// Shareability field
53+
/// Shareability field.
5454
SH OFFSET(8) NUMBITS(2) [
5555
OuterShareable = 0b10,
5656
InnerShareable = 0b11
5757
],
5858

59-
/// Access Permissions
59+
/// Access Permissions.
6060
AP OFFSET(6) NUMBITS(2) [
6161
RW_EL1 = 0b00,
6262
RW_EL1_EL0 = 0b01,
6363
RO_EL1 = 0b10,
6464
RO_EL1_EL0 = 0b11
6565
],
6666

67-
/// Memory attributes index into the MAIR_EL1 register
67+
/// Memory attributes index into the MAIR_EL1 register.
6868
AttrIndx OFFSET(2) NUMBITS(3) [],
6969

7070
TYPE OFFSET(1) NUMBITS(1) [
@@ -150,7 +150,7 @@ impl convert::From<AttributeFields>
150150
for register::FieldValue<u64, STAGE1_PAGE_DESCRIPTOR::Register>
151151
{
152152
fn from(attribute_fields: AttributeFields) -> Self {
153-
// Memory attributes
153+
// Memory attributes.
154154
let mut desc = match attribute_fields.mem_attributes {
155155
MemAttributes::CacheableDRAM => {
156156
STAGE1_PAGE_DESCRIPTOR::SH::InnerShareable
@@ -162,13 +162,13 @@ impl convert::From<AttributeFields>
162162
}
163163
};
164164

165-
// Access Permissions
165+
// Access Permissions.
166166
desc += match attribute_fields.acc_perms {
167167
AccessPermissions::ReadOnly => STAGE1_PAGE_DESCRIPTOR::AP::RO_EL1,
168168
AccessPermissions::ReadWrite => STAGE1_PAGE_DESCRIPTOR::AP::RW_EL1,
169169
};
170170

171-
// Execute Never
171+
// Execute Never.
172172
desc += if attribute_fields.execute_never {
173173
STAGE1_PAGE_DESCRIPTOR::PXN::True
174174
} else {
@@ -204,11 +204,11 @@ mod mair {
204204
fn set_up_mair() {
205205
// Define the memory types being mapped.
206206
MAIR_EL1.write(
207-
// Attribute 1 - Cacheable normal DRAM
207+
// Attribute 1 - Cacheable normal DRAM.
208208
MAIR_EL1::Attr1_HIGH::Memory_OuterWriteBack_NonTransient_ReadAlloc_WriteAlloc
209209
+ MAIR_EL1::Attr1_LOW_MEMORY::InnerWriteBack_NonTransient_ReadAlloc_WriteAlloc
210210

211-
// Attribute 0 - Device
211+
// Attribute 0 - Device.
212212
+ MAIR_EL1::Attr0_HIGH::Device
213213
+ MAIR_EL1::Attr0_LOW_DEVICE::Device_nGnRE,
214214
);
@@ -292,7 +292,7 @@ impl interface::mm::MMU for MMU {
292292
// Enable the MMU and turn on data and instruction caching.
293293
SCTLR_EL1.modify(SCTLR_EL1::M::Enable + SCTLR_EL1::C::Cacheable + SCTLR_EL1::I::Cacheable);
294294

295-
// Force MMU init to complete before next instruction
295+
// Force MMU init to complete before next instruction.
296296
barrier::isb(barrier::SY);
297297

298298
Ok(())

‎12_cpu_exceptions_part1/README.md

+4-4
Original file line numberDiff line numberDiff line change
@@ -474,7 +474,7 @@ diff -uNr 11_virtual_memory/src/arch/aarch64/exception.rs 12_cpu_exceptions_part
474474
+// Assembly counterpart to this file.
475475
+global_asm!(include_str!("exception.S"));
476476
+
477-
+/// Wrapper struct for memory copy of SPSR_EL1
477+
+/// Wrapper struct for memory copy of SPSR_EL1.
478478
+#[repr(transparent)]
479479
+struct SpsrEL1(InMemoryRegister<u32, SPSR_EL1::Register>);
480480
+
@@ -491,7 +491,7 @@ diff -uNr 11_virtual_memory/src/arch/aarch64/exception.rs 12_cpu_exceptions_part
491491
+ spsr_el1: SpsrEL1,
492492
+}
493493
+
494-
+/// Wrapper struct for pretty printing ESR_EL1
494+
+/// Wrapper struct for pretty printing ESR_EL1.
495495
+struct EsrEL1;
496496
+
497497
+//--------------------------------------------------------------------------------------------------
@@ -537,7 +537,7 @@ diff -uNr 11_virtual_memory/src/arch/aarch64/exception.rs 12_cpu_exceptions_part
537537
+/// Asynchronous exception taken from the current EL, using SP of the current EL.
538538
+#[no_mangle]
539539
+unsafe extern "C" fn current_elx_synchronous(e: &mut ExceptionContext) {
540-
+ let far_el1 = FAR_EL1.extract().get();
540+
+ let far_el1 = FAR_EL1.get();
541541
+
542542
+ // This catches the demo case for this tutorial. If the fault address happens to be 8 GiB,
543543
+ // advance the exception link register for one instruction, so that execution can continue.
@@ -697,7 +697,7 @@ diff -uNr 11_virtual_memory/src/arch/aarch64/exception.rs 12_cpu_exceptions_part
697697
+/// - The vector table and the symbol `__exception_vector_table_start` from the linker script must
698698
+/// adhere to the alignment and size constraints demanded by the AArch64 spec.
699699
+pub unsafe fn set_vbar_el1() {
700-
+ // Provided by exception_vec_table.S.
700+
+ // Provided by exception.S.
701701
+ extern "C" {
702702
+ static mut __exception_vector_start: u64;
703703
+ }

‎12_cpu_exceptions_part1/src/arch/aarch64/exception.rs

+4-4
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ use register::InMemoryRegister;
1111
// Assembly counterpart to this file.
1212
global_asm!(include_str!("exception.S"));
1313

14-
/// Wrapper struct for memory copy of SPSR_EL1
14+
/// Wrapper struct for memory copy of SPSR_EL1.
1515
#[repr(transparent)]
1616
struct SpsrEL1(InMemoryRegister<u32, SPSR_EL1::Register>);
1717

@@ -28,7 +28,7 @@ struct ExceptionContext {
2828
spsr_el1: SpsrEL1,
2929
}
3030

31-
/// Wrapper struct for pretty printing ESR_EL1
31+
/// Wrapper struct for pretty printing ESR_EL1.
3232
struct EsrEL1;
3333

3434
//--------------------------------------------------------------------------------------------------
@@ -74,7 +74,7 @@ unsafe extern "C" fn current_el0_serror(e: &mut ExceptionContext) {
7474
/// Asynchronous exception taken from the current EL, using SP of the current EL.
7575
#[no_mangle]
7676
unsafe extern "C" fn current_elx_synchronous(e: &mut ExceptionContext) {
77-
let far_el1 = FAR_EL1.extract().get();
77+
let far_el1 = FAR_EL1.get();
7878

7979
// This catches the demo case for this tutorial. If the fault address happens to be 8 GiB,
8080
// advance the exception link register for one instruction, so that execution can continue.
@@ -234,7 +234,7 @@ impl fmt::Display for ExceptionContext {
234234
/// - The vector table and the symbol `__exception_vector_table_start` from the linker script must
235235
/// adhere to the alignment and size constraints demanded by the AArch64 spec.
236236
pub unsafe fn set_vbar_el1() {
237-
// Provided by exception_vec_table.S.
237+
// Provided by exception.S.
238238
extern "C" {
239239
static mut __exception_vector_start: u64;
240240
}

‎12_cpu_exceptions_part1/src/arch/aarch64/mmu.rs

+11-11
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@ register_bitfields! {u64,
3535
// A level 3 page descriptor, as per AArch64 Reference Manual Figure D4-17.
3636
register_bitfields! {u64,
3737
STAGE1_PAGE_DESCRIPTOR [
38-
/// Privileged execute-never
38+
/// Privileged execute-never.
3939
PXN OFFSET(53) NUMBITS(1) [
4040
False = 0,
4141
True = 1
@@ -44,27 +44,27 @@ register_bitfields! {u64,
4444
/// Physical address of the next page table (lvl2) or the page descriptor (lvl3).
4545
OUTPUT_ADDR_64KiB OFFSET(16) NUMBITS(32) [], // [47:16]
4646

47-
/// Access flag
47+
/// Access flag.
4848
AF OFFSET(10) NUMBITS(1) [
4949
False = 0,
5050
True = 1
5151
],
5252

53-
/// Shareability field
53+
/// Shareability field.
5454
SH OFFSET(8) NUMBITS(2) [
5555
OuterShareable = 0b10,
5656
InnerShareable = 0b11
5757
],
5858

59-
/// Access Permissions
59+
/// Access Permissions.
6060
AP OFFSET(6) NUMBITS(2) [
6161
RW_EL1 = 0b00,
6262
RW_EL1_EL0 = 0b01,
6363
RO_EL1 = 0b10,
6464
RO_EL1_EL0 = 0b11
6565
],
6666

67-
/// Memory attributes index into the MAIR_EL1 register
67+
/// Memory attributes index into the MAIR_EL1 register.
6868
AttrIndx OFFSET(2) NUMBITS(3) [],
6969

7070
TYPE OFFSET(1) NUMBITS(1) [
@@ -150,7 +150,7 @@ impl convert::From<AttributeFields>
150150
for register::FieldValue<u64, STAGE1_PAGE_DESCRIPTOR::Register>
151151
{
152152
fn from(attribute_fields: AttributeFields) -> Self {
153-
// Memory attributes
153+
// Memory attributes.
154154
let mut desc = match attribute_fields.mem_attributes {
155155
MemAttributes::CacheableDRAM => {
156156
STAGE1_PAGE_DESCRIPTOR::SH::InnerShareable
@@ -162,13 +162,13 @@ impl convert::From<AttributeFields>
162162
}
163163
};
164164

165-
// Access Permissions
165+
// Access Permissions.
166166
desc += match attribute_fields.acc_perms {
167167
AccessPermissions::ReadOnly => STAGE1_PAGE_DESCRIPTOR::AP::RO_EL1,
168168
AccessPermissions::ReadWrite => STAGE1_PAGE_DESCRIPTOR::AP::RW_EL1,
169169
};
170170

171-
// Execute Never
171+
// Execute Never.
172172
desc += if attribute_fields.execute_never {
173173
STAGE1_PAGE_DESCRIPTOR::PXN::True
174174
} else {
@@ -204,11 +204,11 @@ mod mair {
204204
fn set_up_mair() {
205205
// Define the memory types being mapped.
206206
MAIR_EL1.write(
207-
// Attribute 1 - Cacheable normal DRAM
207+
// Attribute 1 - Cacheable normal DRAM.
208208
MAIR_EL1::Attr1_HIGH::Memory_OuterWriteBack_NonTransient_ReadAlloc_WriteAlloc
209209
+ MAIR_EL1::Attr1_LOW_MEMORY::InnerWriteBack_NonTransient_ReadAlloc_WriteAlloc
210210

211-
// Attribute 0 - Device
211+
// Attribute 0 - Device.
212212
+ MAIR_EL1::Attr0_HIGH::Device
213213
+ MAIR_EL1::Attr0_LOW_DEVICE::Device_nGnRE,
214214
);
@@ -292,7 +292,7 @@ impl interface::mm::MMU for MMU {
292292
// Enable the MMU and turn on data and instruction caching.
293293
SCTLR_EL1.modify(SCTLR_EL1::M::Enable + SCTLR_EL1::C::Cacheable + SCTLR_EL1::I::Cacheable);
294294

295-
// Force MMU init to complete before next instruction
295+
// Force MMU init to complete before next instruction.
296296
barrier::isb(barrier::SY);
297297

298298
Ok(())

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