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Add interrupts and exceptions to link.x only when required
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6 files changed

+88
-55
lines changed

6 files changed

+88
-55
lines changed

‎riscv-rt/CHANGELOG.md

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Original file line numberDiff line numberDiff line change
@@ -7,6 +7,13 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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## [Unreleased]
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### Changed
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- Linker file now refers to standard exceptions and interrupts only when the
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`no-exceptions` and `no-interrupts` features are disabled, respectively.
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This is achieved by substituting `${INCLUDE_LINKER_FILES}` with the contents
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of `exceptions.x` and/or `interrupts.x`.
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## [v0.14.0] - 2025-02-18
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### Changed

‎riscv-rt/build.rs

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Original file line numberDiff line numberDiff line change
@@ -11,9 +11,24 @@ fn add_linker_script(arch_width: u32) -> io::Result<()> {
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let mut content = fs::read_to_string("link.x.in")?;
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content = content.replace("${ARCH_WIDTH}", &arch_width.to_string());
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let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap());
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// Get target-dependent linker configuration and replace ${INCLUDE_LINKER_FILES} with it
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let mut include_content = String::new();
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// If no-exceptions is disabled, include the exceptions.x files
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if env::var_os("CARGO_FEATURE_NO_EXCEPTIONS").is_none() {
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let exceptions_content = fs::read_to_string("exceptions.x")?;
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include_content.push_str(&(exceptions_content + "\n"));
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}
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// If no-interrupts is disabled, include the interrupts.x files
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if env::var_os("CARGO_FEATURE_NO_INTERRUPTS").is_none() {
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let interrupts_content = fs::read_to_string("interrupts.x")?;
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include_content.push_str(&(interrupts_content + "\n"));
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}
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content = content.replace("${INCLUDE_LINKER_FILES}", &include_content);
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// Put the linker script somewhere the linker can find it
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let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap());
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fs::write(out_dir.join("link.x"), content)?;
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println!("cargo:rustc-link-search={}", out_dir.display());
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println!("cargo:rerun-if-changed=link.x");

‎riscv-rt/exceptions.x

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@@ -0,0 +1,23 @@
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/* # EXCEPTION HANDLERS DESCRIBED IN THE STANDARD RISC-V ISA
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If the `no-exceptions` feature is DISABLED, this file will be included in link.x.in.
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If the `no-exceptions` feature is ENABLED, this file will be ignored.
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*/
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/* It is possible to define a special handler for each exception type.
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By default, all exceptions are handled by ExceptionHandler. However,
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users can override these alias by defining the symbol themselves */
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PROVIDE(InstructionMisaligned = ExceptionHandler);
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PROVIDE(InstructionFault = ExceptionHandler);
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PROVIDE(IllegalInstruction = ExceptionHandler);
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PROVIDE(Breakpoint = ExceptionHandler);
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PROVIDE(LoadMisaligned = ExceptionHandler);
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PROVIDE(LoadFault = ExceptionHandler);
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PROVIDE(StoreMisaligned = ExceptionHandler);
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PROVIDE(StoreFault = ExceptionHandler);
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PROVIDE(UserEnvCall = ExceptionHandler);
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PROVIDE(SupervisorEnvCall = ExceptionHandler);
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PROVIDE(MachineEnvCall = ExceptionHandler);
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PROVIDE(InstructionPageFault = ExceptionHandler);
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PROVIDE(LoadPageFault = ExceptionHandler);
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PROVIDE(StorePageFault = ExceptionHandler);

‎riscv-rt/interrupts.x

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
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/* # CORE INTERRUPT HANDLERS DESCRIBED IN THE STANDARD RISC-V ISA
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If the `no-interrupts` feature is DISABLED, this file will be included in link.x.in.
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If the `no-interrupts` feature is ENABLED, this file will be ignored.
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*/
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/* It is possible to define a special handler for each interrupt type.
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By default, all interrupts are handled by DefaultHandler. However, users can
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override these alias by defining the symbol themselves */
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PROVIDE(SupervisorSoft = DefaultHandler);
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PROVIDE(MachineSoft = DefaultHandler);
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PROVIDE(SupervisorTimer = DefaultHandler);
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PROVIDE(MachineTimer = DefaultHandler);
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PROVIDE(SupervisorExternal = DefaultHandler);
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PROVIDE(MachineExternal = DefaultHandler);
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/* When vectored trap mode is enabled, each interrupt source must implement its own
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trap entry point. By default, all interrupts start in _DefaultHandler_trap.
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However, users can override these alias by defining the symbol themselves */
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PROVIDE(_start_SupervisorSoft_trap = _start_DefaultHandler_trap);
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PROVIDE(_start_MachineSoft_trap = _start_DefaultHandler_trap);
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PROVIDE(_start_SupervisorTimer_trap = _start_DefaultHandler_trap);
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PROVIDE(_start_MachineTimer_trap = _start_DefaultHandler_trap);
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PROVIDE(_start_SupervisorExternal_trap = _start_DefaultHandler_trap);
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PROVIDE(_start_MachineExternal_trap = _start_DefaultHandler_trap);

‎riscv-rt/link.x.in

+14-54
Original file line numberDiff line numberDiff line change
@@ -22,73 +22,33 @@
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means that you won't see "Address (..) is out of bounds" in the disassembly produced by `objdump`.
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*/
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PROVIDE(_stext = ORIGIN(REGION_TEXT));
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PROVIDE(_stack_start = ORIGIN(REGION_STACK) + LENGTH(REGION_STACK));
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PROVIDE(_max_hart_id = 0);
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PROVIDE(_hart_stack_size = 2K);
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PROVIDE(_heap_size = 0);
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/** TRAP ENTRY POINTS **/
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/* Default trap entry point. The riscv-rt crate provides a weak alias of this function,
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which saves caller saved registers, calls _start_trap_rust, restores caller saved registers
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and then returns. Users can override this alias by defining the symbol themselves */
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EXTERN(_start_trap);
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38-
/* Default interrupt trap entry point. When vectored trap mode is enabled,
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the riscv-rt crate provides an implementation of this function, which saves caller saved
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registers, calls the the DefaultHandler ISR, restores caller saved registers and returns. */
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PROVIDE(_start_DefaultHandler_trap = _start_trap);
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/* When vectored trap mode is enabled, each interrupt source must implement its own
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trap entry point. By default, all interrupts start in _start_trap. However, users can
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override these alias by defining the symbol themselves */
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PROVIDE(_start_SupervisorSoft_trap = _start_DefaultHandler_trap);
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PROVIDE(_start_MachineSoft_trap = _start_DefaultHandler_trap);
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PROVIDE(_start_SupervisorTimer_trap = _start_DefaultHandler_trap);
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PROVIDE(_start_MachineTimer_trap = _start_DefaultHandler_trap);
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PROVIDE(_start_SupervisorExternal_trap = _start_DefaultHandler_trap);
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PROVIDE(_start_MachineExternal_trap = _start_DefaultHandler_trap);
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/** EXCEPTION HANDLERS **/
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/* Default exception handler. The riscv-rt crate provides a weak alias of this function,
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which is a busy loop. Users can override this alias by defining the symbol themselves */
5732
EXTERN(ExceptionHandler);
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59-
/* It is possible to define a special handler for each exception type.
60-
By default, all exceptions are handled by ExceptionHandler. However, users can
61-
override these alias by defining the symbol themselves */
62-
PROVIDE(InstructionMisaligned = ExceptionHandler);
63-
PROVIDE(InstructionFault = ExceptionHandler);
64-
PROVIDE(IllegalInstruction = ExceptionHandler);
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PROVIDE(Breakpoint = ExceptionHandler);
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PROVIDE(LoadMisaligned = ExceptionHandler);
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PROVIDE(LoadFault = ExceptionHandler);
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PROVIDE(StoreMisaligned = ExceptionHandler);
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PROVIDE(StoreFault = ExceptionHandler);
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PROVIDE(UserEnvCall = ExceptionHandler);
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PROVIDE(SupervisorEnvCall = ExceptionHandler);
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PROVIDE(MachineEnvCall = ExceptionHandler);
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PROVIDE(InstructionPageFault = ExceptionHandler);
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PROVIDE(LoadPageFault = ExceptionHandler);
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PROVIDE(StorePageFault = ExceptionHandler);
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77-
/** INTERRUPT HANDLERS **/
78-
7934
/* Default interrupt handler. The riscv-rt crate provides a weak alias of this function,
8035
which is a busy loop. Users can override this alias by defining the symbol themselves */
8136
EXTERN(DefaultHandler);
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83-
/* It is possible to define a special handler for each interrupt type.
84-
By default, all interrupts are handled by DefaultHandler. However, users can
85-
override these alias by defining the symbol themselves */
86-
PROVIDE(SupervisorSoft = DefaultHandler);
87-
PROVIDE(MachineSoft = DefaultHandler);
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PROVIDE(SupervisorTimer = DefaultHandler);
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PROVIDE(MachineTimer = DefaultHandler);
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PROVIDE(SupervisorExternal = DefaultHandler);
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PROVIDE(MachineExternal = DefaultHandler);
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/* Default interrupt trap entry point. When vectored trap mode is enabled,
39+
the riscv-rt crate provides an implementation of this function, which saves caller saved
40+
registers, calls the the DefaultHandler ISR, restores caller saved registers and returns.
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Note, however, that this provided implementation cannot be overwritten. We use PROVIDE
42+
to avoid compilation errors in direct mode, not to allow users to overwrite the symbol. */
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PROVIDE(_start_DefaultHandler_trap = _start_trap);
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${INCLUDE_LINKER_FILES}
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PROVIDE(_stext = ORIGIN(REGION_TEXT));
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PROVIDE(_stack_start = ORIGIN(REGION_STACK) + LENGTH(REGION_STACK));
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PROVIDE(_max_hart_id = 0);
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PROVIDE(_hart_stack_size = 2K);
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PROVIDE(_heap_size = 0);
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SECTIONS
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{

‎tests/Cargo.toml

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@@ -7,3 +7,6 @@ edition = "2021"
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riscv = { path = "../riscv", version = "0.13.0" }
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riscv-rt = { path = "../riscv-rt", version = "0.14.0", features = ["no-exceptions", "no-interrupts"]}
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trybuild = "1.0"
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[features]
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v-trap = ["riscv-rt/v-trap"]

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