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‎src/adc.rs

+11-20
Original file line numberDiff line numberDiff line change
@@ -32,10 +32,7 @@ impl RegisterBlock {
3232
pub const fn fifo(&self) -> &FIFO {
3333
&self.fifo
3434
}
35-
#[doc = "0x10 - Clock divider. If non-zero, CS_START_MANY will start conversions
36-
at regular intervals rather than back-to-back.
37-
The divider is reset when either of these fields are written.
38-
Total period is 1 + INT + FRAC / 256"]
35+
#[doc = "0x10 - Clock divider. If non-zero, CS_START_MANY will start conversions at regular intervals rather than back-to-back. The divider is reset when either of these fields are written. Total period is 1 + INT + FRAC / 256"]
3936
#[inline(always)]
4037
pub const fn div(&self) -> &DIV {
4138
&self.div
@@ -70,9 +67,9 @@ module"]
7067
pub type CS = crate::Reg<cs::CS_SPEC>;
7168
#[doc = "ADC Control and Status"]
7269
pub mod cs;
73-
#[doc = "RESULT (r) register accessor: Result of most recent ADC conversion
70+
#[doc = "RESULT (rw) register accessor: Result of most recent ADC conversion
7471
75-
You can [`read`](crate::generic::Reg::read) this register and get [`result::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
72+
You can [`read`](crate::generic::Reg::read) this register and get [`result::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`result::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
7673
7774
For information about available fields see [`mod@result`]
7875
module"]
@@ -88,33 +85,27 @@ module"]
8885
pub type FCS = crate::Reg<fcs::FCS_SPEC>;
8986
#[doc = "FIFO control and status"]
9087
pub mod fcs;
91-
#[doc = "FIFO (r) register accessor: Conversion result FIFO
88+
#[doc = "FIFO (rw) register accessor: Conversion result FIFO
9289
93-
You can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
90+
You can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
9491
9592
For information about available fields see [`mod@fifo`]
9693
module"]
9794
pub type FIFO = crate::Reg<fifo::FIFO_SPEC>;
9895
#[doc = "Conversion result FIFO"]
9996
pub mod fifo;
100-
#[doc = "DIV (rw) register accessor: Clock divider. If non-zero, CS_START_MANY will start conversions
101-
at regular intervals rather than back-to-back.
102-
The divider is reset when either of these fields are written.
103-
Total period is 1 + INT + FRAC / 256
97+
#[doc = "DIV (rw) register accessor: Clock divider. If non-zero, CS_START_MANY will start conversions at regular intervals rather than back-to-back. The divider is reset when either of these fields are written. Total period is 1 + INT + FRAC / 256
10498
10599
You can [`read`](crate::generic::Reg::read) this register and get [`div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
106100
107101
For information about available fields see [`mod@div`]
108102
module"]
109103
pub type DIV = crate::Reg<div::DIV_SPEC>;
110-
#[doc = "Clock divider. If non-zero, CS_START_MANY will start conversions
111-
at regular intervals rather than back-to-back.
112-
The divider is reset when either of these fields are written.
113-
Total period is 1 + INT + FRAC / 256"]
104+
#[doc = "Clock divider. If non-zero, CS_START_MANY will start conversions at regular intervals rather than back-to-back. The divider is reset when either of these fields are written. Total period is 1 + INT + FRAC / 256"]
114105
pub mod div;
115-
#[doc = "INTR (r) register accessor: Raw Interrupts
106+
#[doc = "INTR (rw) register accessor: Raw Interrupts
116107
117-
You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
108+
You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
118109
119110
For information about available fields see [`mod@intr`]
120111
module"]
@@ -139,9 +130,9 @@ module"]
139130
pub type INTF = crate::Reg<intf::INTF_SPEC>;
140131
#[doc = "Interrupt Force"]
141132
pub mod intf;
142-
#[doc = "INTS (r) register accessor: Interrupt status after masking &amp; forcing
133+
#[doc = "INTS (rw) register accessor: Interrupt status after masking &amp; forcing
143134
144-
You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
135+
You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ints::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
145136
146137
For information about available fields see [`mod@ints`]
147138
module"]

‎src/adc/cs.rs

+10-35
Original file line numberDiff line numberDiff line change
@@ -2,26 +2,21 @@
22
pub type R = crate::R<CS_SPEC>;
33
#[doc = "Register `CS` writer"]
44
pub type W = crate::W<CS_SPEC>;
5-
#[doc = "Field `EN` reader - Power on ADC and enable its clock.
6-
1 - enabled. 0 - disabled."]
5+
#[doc = "Field `EN` reader - Power on ADC and enable its clock. 1 - enabled. 0 - disabled."]
76
pub type EN_R = crate::BitReader;
8-
#[doc = "Field `EN` writer - Power on ADC and enable its clock.
9-
1 - enabled. 0 - disabled."]
7+
#[doc = "Field `EN` writer - Power on ADC and enable its clock. 1 - enabled. 0 - disabled."]
108
pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>;
119
#[doc = "Field `TS_EN` reader - Power on temperature sensor. 1 - enabled. 0 - disabled."]
1210
pub type TS_EN_R = crate::BitReader;
1311
#[doc = "Field `TS_EN` writer - Power on temperature sensor. 1 - enabled. 0 - disabled."]
1412
pub type TS_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
15-
#[doc = "Field `START_ONCE` reader - Start a single conversion. Self-clearing. Ignored if start_many is asserted."]
16-
pub type START_ONCE_R = crate::BitReader;
1713
#[doc = "Field `START_ONCE` writer - Start a single conversion. Self-clearing. Ignored if start_many is asserted."]
1814
pub type START_ONCE_W<'a, REG> = crate::BitWriter<'a, REG>;
1915
#[doc = "Field `START_MANY` reader - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes."]
2016
pub type START_MANY_R = crate::BitReader;
2117
#[doc = "Field `START_MANY` writer - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes."]
2218
pub type START_MANY_W<'a, REG> = crate::BitWriter<'a, REG>;
23-
#[doc = "Field `READY` reader - 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed.
24-
0 whilst conversion in progress."]
19+
#[doc = "Field `READY` reader - 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed. 0 whilst conversion in progress."]
2520
pub type READY_R = crate::BitReader;
2621
#[doc = "Field `ERR` reader - The most recent ADC conversion encountered an error; result is undefined or noisy."]
2722
pub type ERR_R = crate::BitReader;
@@ -33,19 +28,12 @@ pub type ERR_STICKY_W<'a, REG> = crate::BitWriter1C<'a, REG>;
3328
pub type AINSEL_R = crate::FieldReader;
3429
#[doc = "Field `AINSEL` writer - Select analog mux input. Updated automatically in round-robin mode."]
3530
pub type AINSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
36-
#[doc = "Field `RROBIN` reader - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.
37-
Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion.
38-
The first channel to be sampled will be the one currently indicated by AINSEL.
39-
AINSEL will be updated after each conversion with the newly-selected channel."]
31+
#[doc = "Field `RROBIN` reader - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. The first channel to be sampled will be the one currently indicated by AINSEL. AINSEL will be updated after each conversion with the newly-selected channel."]
4032
pub type RROBIN_R = crate::FieldReader;
41-
#[doc = "Field `RROBIN` writer - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.
42-
Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion.
43-
The first channel to be sampled will be the one currently indicated by AINSEL.
44-
AINSEL will be updated after each conversion with the newly-selected channel."]
33+
#[doc = "Field `RROBIN` writer - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. The first channel to be sampled will be the one currently indicated by AINSEL. AINSEL will be updated after each conversion with the newly-selected channel."]
4534
pub type RROBIN_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
4635
impl R {
47-
#[doc = "Bit 0 - Power on ADC and enable its clock.
48-
1 - enabled. 0 - disabled."]
36+
#[doc = "Bit 0 - Power on ADC and enable its clock. 1 - enabled. 0 - disabled."]
4937
#[inline(always)]
5038
pub fn en(&self) -> EN_R {
5139
EN_R::new((self.bits & 1) != 0)
@@ -55,18 +43,12 @@ impl R {
5543
pub fn ts_en(&self) -> TS_EN_R {
5644
TS_EN_R::new(((self.bits >> 1) & 1) != 0)
5745
}
58-
#[doc = "Bit 2 - Start a single conversion. Self-clearing. Ignored if start_many is asserted."]
59-
#[inline(always)]
60-
pub fn start_once(&self) -> START_ONCE_R {
61-
START_ONCE_R::new(((self.bits >> 2) & 1) != 0)
62-
}
6346
#[doc = "Bit 3 - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes."]
6447
#[inline(always)]
6548
pub fn start_many(&self) -> START_MANY_R {
6649
START_MANY_R::new(((self.bits >> 3) & 1) != 0)
6750
}
68-
#[doc = "Bit 8 - 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed.
69-
0 whilst conversion in progress."]
51+
#[doc = "Bit 8 - 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed. 0 whilst conversion in progress."]
7052
#[inline(always)]
7153
pub fn ready(&self) -> READY_R {
7254
READY_R::new(((self.bits >> 8) & 1) != 0)
@@ -86,18 +68,14 @@ impl R {
8668
pub fn ainsel(&self) -> AINSEL_R {
8769
AINSEL_R::new(((self.bits >> 12) & 7) as u8)
8870
}
89-
#[doc = "Bits 16:20 - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.
90-
Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion.
91-
The first channel to be sampled will be the one currently indicated by AINSEL.
92-
AINSEL will be updated after each conversion with the newly-selected channel."]
71+
#[doc = "Bits 16:20 - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. The first channel to be sampled will be the one currently indicated by AINSEL. AINSEL will be updated after each conversion with the newly-selected channel."]
9372
#[inline(always)]
9473
pub fn rrobin(&self) -> RROBIN_R {
9574
RROBIN_R::new(((self.bits >> 16) & 0x1f) as u8)
9675
}
9776
}
9877
impl W {
99-
#[doc = "Bit 0 - Power on ADC and enable its clock.
100-
1 - enabled. 0 - disabled."]
78+
#[doc = "Bit 0 - Power on ADC and enable its clock. 1 - enabled. 0 - disabled."]
10179
#[inline(always)]
10280
#[must_use]
10381
pub fn en(&mut self) -> EN_W<CS_SPEC> {
@@ -133,10 +111,7 @@ impl W {
133111
pub fn ainsel(&mut self) -> AINSEL_W<CS_SPEC> {
134112
AINSEL_W::new(self, 12)
135113
}
136-
#[doc = "Bits 16:20 - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.
137-
Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion.
138-
The first channel to be sampled will be the one currently indicated by AINSEL.
139-
AINSEL will be updated after each conversion with the newly-selected channel."]
114+
#[doc = "Bits 16:20 - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. The first channel to be sampled will be the one currently indicated by AINSEL. AINSEL will be updated after each conversion with the newly-selected channel."]
140115
#[inline(always)]
141116
#[must_use]
142117
pub fn rrobin(&mut self) -> RROBIN_W<CS_SPEC> {

‎src/adc/div.rs

+1-4
Original file line numberDiff line numberDiff line change
@@ -36,10 +36,7 @@ impl W {
3636
INT_W::new(self, 8)
3737
}
3838
}
39-
#[doc = "Clock divider. If non-zero, CS_START_MANY will start conversions
40-
at regular intervals rather than back-to-back.
41-
The divider is reset when either of these fields are written.
42-
Total period is 1 + INT + FRAC / 256
39+
#[doc = "Clock divider. If non-zero, CS_START_MANY will start conversions at regular intervals rather than back-to-back. The divider is reset when either of these fields are written. Total period is 1 + INT + FRAC / 256
4340
4441
You can [`read`](crate::generic::Reg::read) this register and get [`div::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
4542
pub struct DIV_SPEC;

‎src/adc/fifo.rs

+16-3
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,14 @@
11
#[doc = "Register `FIFO` reader"]
22
pub type R = crate::R<FIFO_SPEC>;
3-
#[doc = "Field `VAL` reader - "]
3+
#[doc = "Register `FIFO` writer"]
4+
pub type W = crate::W<FIFO_SPEC>;
5+
#[doc = "Field `VAL` reader -
6+
7+
The field is **modified** in some way after a read operation."]
48
pub type VAL_R = crate::FieldReader<u16>;
5-
#[doc = "Field `ERR` reader - 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted."]
9+
#[doc = "Field `ERR` reader - 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted.
10+
11+
The field is **modified** in some way after a read operation."]
612
pub type ERR_R = crate::BitReader;
713
impl R {
814
#[doc = "Bits 0:11"]
@@ -16,15 +22,22 @@ impl R {
1622
ERR_R::new(((self.bits >> 15) & 1) != 0)
1723
}
1824
}
25+
impl W {}
1926
#[doc = "Conversion result FIFO
2027
21-
You can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
28+
You can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
2229
pub struct FIFO_SPEC;
2330
impl crate::RegisterSpec for FIFO_SPEC {
2431
type Ux = u32;
2532
}
2633
#[doc = "`read()` method returns [`fifo::R`](R) reader structure"]
2734
impl crate::Readable for FIFO_SPEC {}
35+
#[doc = "`write(|w| ..)` method takes [`fifo::W`](W) writer structure"]
36+
impl crate::Writable for FIFO_SPEC {
37+
type Safety = crate::Unsafe;
38+
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
39+
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
40+
}
2841
#[doc = "`reset()` method sets FIFO to value 0"]
2942
impl crate::Resettable for FIFO_SPEC {
3043
const RESET_VALUE: u32 = 0;

‎src/adc/inte.rs

+4-8
Original file line numberDiff line numberDiff line change
@@ -2,23 +2,19 @@
22
pub type R = crate::R<INTE_SPEC>;
33
#[doc = "Register `INTE` writer"]
44
pub type W = crate::W<INTE_SPEC>;
5-
#[doc = "Field `FIFO` reader - Triggered when the sample FIFO reaches a certain level.
6-
This level can be programmed via the FCS_THRESH field."]
5+
#[doc = "Field `FIFO` reader - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."]
76
pub type FIFO_R = crate::BitReader;
8-
#[doc = "Field `FIFO` writer - Triggered when the sample FIFO reaches a certain level.
9-
This level can be programmed via the FCS_THRESH field."]
7+
#[doc = "Field `FIFO` writer - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."]
108
pub type FIFO_W<'a, REG> = crate::BitWriter<'a, REG>;
119
impl R {
12-
#[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level.
13-
This level can be programmed via the FCS_THRESH field."]
10+
#[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."]
1411
#[inline(always)]
1512
pub fn fifo(&self) -> FIFO_R {
1613
FIFO_R::new((self.bits & 1) != 0)
1714
}
1815
}
1916
impl W {
20-
#[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level.
21-
This level can be programmed via the FCS_THRESH field."]
17+
#[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."]
2218
#[inline(always)]
2319
#[must_use]
2420
pub fn fifo(&mut self) -> FIFO_W<INTE_SPEC> {

‎src/adc/intf.rs

+4-8
Original file line numberDiff line numberDiff line change
@@ -2,23 +2,19 @@
22
pub type R = crate::R<INTF_SPEC>;
33
#[doc = "Register `INTF` writer"]
44
pub type W = crate::W<INTF_SPEC>;
5-
#[doc = "Field `FIFO` reader - Triggered when the sample FIFO reaches a certain level.
6-
This level can be programmed via the FCS_THRESH field."]
5+
#[doc = "Field `FIFO` reader - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."]
76
pub type FIFO_R = crate::BitReader;
8-
#[doc = "Field `FIFO` writer - Triggered when the sample FIFO reaches a certain level.
9-
This level can be programmed via the FCS_THRESH field."]
7+
#[doc = "Field `FIFO` writer - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."]
108
pub type FIFO_W<'a, REG> = crate::BitWriter<'a, REG>;
119
impl R {
12-
#[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level.
13-
This level can be programmed via the FCS_THRESH field."]
10+
#[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."]
1411
#[inline(always)]
1512
pub fn fifo(&self) -> FIFO_R {
1613
FIFO_R::new((self.bits & 1) != 0)
1714
}
1815
}
1916
impl W {
20-
#[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level.
21-
This level can be programmed via the FCS_THRESH field."]
17+
#[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."]
2218
#[inline(always)]
2319
#[must_use]
2420
pub fn fifo(&mut self) -> FIFO_W<INTF_SPEC> {

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