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21 | 21 | from enum import Enum
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22 | 22 | from typing import (List, Optional, Sequence, Tuple, Union)
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23 | 23 | import usb.core
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| 24 | +import time |
| 25 | + |
24 | 26 |
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25 | 27 | from .constants import (Commands, Status, SWD_FREQ_MAP, JTAG_FREQ_MAP)
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26 | 28 | from ...core import exceptions
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@@ -470,11 +472,20 @@ def _write_mem(self, addr: int, data: Sequence[int], memcmd: int, maxtx: int, ap
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470 | 472 |
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471 | 473 | def read_mem32(self, addr: int, size: int, apsel: int, csw: int):
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472 | 474 | assert (addr & 0x3) == 0 and (size & 0x3) == 0, "address and size must be word aligned"
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473 |
| - return self._read_mem(addr, size, Commands.JTAG_READMEM_32BIT, self.MAXIMUM_TRANSFER_SIZE, apsel, csw) |
| 475 | + for attempt in range(10): |
| 476 | + try: |
| 477 | + return self._read_mem(addr, size, Commands.JTAG_READMEM_32BIT, self.MAXIMUM_TRANSFER_SIZE, apsel, csw) |
| 478 | + except: |
| 479 | + time.sleep(0.1) |
474 | 480 |
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475 | 481 | def write_mem32(self, addr: int, data: Sequence[int], apsel: int, csw: int):
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476 | 482 | assert (addr & 0x3) == 0 and (len(data) & 3) == 0, "address and size must be word aligned"
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477 |
| - self._write_mem(addr, data, Commands.JTAG_WRITEMEM_32BIT, self.MAXIMUM_TRANSFER_SIZE, apsel, csw) |
| 483 | + for attempt in range(10): |
| 484 | + try: |
| 485 | + self._write_mem(addr, data, Commands.JTAG_WRITEMEM_32BIT, self.MAXIMUM_TRANSFER_SIZE, apsel, csw) |
| 486 | + return |
| 487 | + except: |
| 488 | + time.sleep(0.1) |
478 | 489 |
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479 | 490 | def read_mem16(self, addr: int, size: int, apsel: int, csw: int):
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480 | 491 | assert (addr & 0x1) == 0 and (size & 0x1) == 0, "address and size must be half-word aligned"
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