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MarioOpenHWGroupMarioOpenHWGroup
authoredFeb 26, 2024
add RVFI CSRs tracing (#184)
1 parent 00bad97 commit 1786fbf

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4 files changed

+167
-11
lines changed

4 files changed

+167
-11
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‎rtl/cve2_core.sv

+8-7
Original file line numberDiff line numberDiff line change
@@ -625,14 +625,12 @@ module cve2_core import cve2_pkg::*; #(
625625
assign outstanding_store_id = id_stage_i.instr_executing & id_stage_i.lsu_req_dec &
626626
id_stage_i.lsu_we;
627627

628-
begin : gen_no_wb_stage
629-
// Without writeback stage only look into whether load or store is in ID to determine if
630-
// a response is expected.
631-
assign outstanding_load_resp = outstanding_load_id;
632-
assign outstanding_store_resp = outstanding_store_id;
628+
// Without writeback stage only look into whether load or store is in ID to determine if
629+
// a response is expected.
630+
assign outstanding_load_resp = outstanding_load_id;
631+
assign outstanding_store_resp = outstanding_store_id;
633632

634-
`ASSERT(NoMemRFWriteWithoutPendingLoad, rf_we_lsu |-> outstanding_load_id, clk_i, !rst_ni)
635-
end
633+
`ASSERT(NoMemRFWriteWithoutPendingLoad, rf_we_lsu |-> outstanding_load_id, clk_i, !rst_ni)
636634

637635
`ASSERT(NoMemResponseWithoutPendingAccess,
638636
data_rvalid_i |-> outstanding_load_resp | outstanding_store_resp, clk_i, !rst_ni)
@@ -1094,6 +1092,9 @@ module cve2_core import cve2_pkg::*; #(
10941092
rvfi_ext_stage_debug_req[i+1] <= rvfi_ext_stage_debug_req[i];
10951093
rvfi_ext_stage_mcycle[i] <= cs_registers_i.mcycle_counter_i.counter_val_o;
10961094
end
1095+
else begin
1096+
rvfi_stage_trap[i] <= 0;
1097+
end
10971098
end else begin
10981099
rvfi_stage_halt[i] <= rvfi_stage_halt[i-1];
10991100
rvfi_stage_trap[i] <= rvfi_stage_trap[i-1];

‎rtl/cve2_cs_registers.sv

+79-2
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,7 @@ module cve2_cs_registers #(
2424
parameter cve2_pkg::rv32m_e RV32M = cve2_pkg::RV32MFast,
2525
parameter cve2_pkg::rv32b_e RV32B = cve2_pkg::RV32BNone
2626
) (
27+
2728
// Clock and Reset
2829
input logic clk_i,
2930
input logic rst_ni,
@@ -103,7 +104,7 @@ module cve2_cs_registers #(
103104
input logic div_wait_i // core waiting for divide
104105
);
105106

106-
import cve2_pkg::*;
107+
import cve2_pkg::*;
107108

108109
localparam int unsigned RV32BEnabled = (RV32B == RV32BNone) ? 0 : 1;
109110
localparam int unsigned RV32MEnabled = (RV32M == RV32MNone) ? 0 : 1;
@@ -1444,7 +1445,83 @@ module cve2_cs_registers #(
14441445
// CPU control register //
14451446
//////////////////////////
14461447

1447-
// Removed
1448+
`ifdef RVFI
1449+
logic [63:0] mstatus_extended_read;
1450+
logic [63:0] mstatus_extended_write;
1451+
1452+
assign mstatus_extended_read[CSR_MSTATUS_MIE_BIT] = mstatus_q.mie;
1453+
assign mstatus_extended_read[CSR_MSTATUS_MPIE_BIT] = mstatus_q.mpie;
1454+
assign mstatus_extended_read[CSR_MSTATUS_MPP_BIT_HIGH:CSR_MSTATUS_MPP_BIT_LOW] = mstatus_q.mpp;
1455+
assign mstatus_extended_read[CSR_MSTATUS_MPRV_BIT] = mstatus_q.mprv;
1456+
assign mstatus_extended_read[CSR_MSTATUS_TW_BIT] = mstatus_q.tw;
1457+
1458+
assign mstatus_extended_write[CSR_MSTATUS_MIE_BIT] = mstatus_d.mie;
1459+
assign mstatus_extended_write[CSR_MSTATUS_MPIE_BIT] = mstatus_d.mpie;
1460+
assign mstatus_extended_write[CSR_MSTATUS_MPP_BIT_HIGH:CSR_MSTATUS_MPP_BIT_LOW] = mstatus_d.mpp;
1461+
assign mstatus_extended_write[CSR_MSTATUS_MPRV_BIT] = mstatus_d.mprv;
1462+
assign mstatus_extended_write[CSR_MSTATUS_TW_BIT] = mstatus_d.tw;
1463+
1464+
wire [63:0] rvfi_csr_bypass;
1465+
1466+
assign rvfi_csr_bypass = csr_save_cause_i;
1467+
1468+
bit [63:0] rvfi_csr_addr;
1469+
bit [63:0] rvfi_csr_rdata;
1470+
bit [63:0] rvfi_csr_wdata;
1471+
bit [63:0] rvfi_csr_rmask;
1472+
bit [63:0] rvfi_csr_wmask;
1473+
wire [63:0] rvfi_csr_wmask_q;
1474+
wire [63:0] rvfi_csr_rmask_q;
1475+
assign rvfi_csr_if.rvfi_csr_addr = rvfi_csr_addr;
1476+
assign rvfi_csr_if.rvfi_csr_rdata = rvfi_csr_rdata;
1477+
assign rvfi_csr_if.rvfi_csr_wdata = rvfi_csr_wdata;
1478+
assign rvfi_csr_if.rvfi_csr_rmask = rvfi_csr_rmask;
1479+
assign rvfi_csr_if.rvfi_csr_wmask = rvfi_csr_wmask;
1480+
assign rvfi_csr_rmask_q = ((~csr_wr & csr_op_en_i & ~illegal_csr_insn_o)) ? -1 : 0;
1481+
assign rvfi_csr_wmask_q = ((csr_wr & csr_op_en_i & ~illegal_csr_insn_o)) ? -1 : 0;
1482+
always @(posedge clknrst_if.clk) begin
1483+
rvfi_csr_addr = csr_addr_i;
1484+
rvfi_csr_rdata = csr_rdata_int;
1485+
rvfi_csr_wdata = csr_wdata_int;
1486+
rvfi_csr_rmask = (rvfi_csr_rmask_q);
1487+
rvfi_csr_wmask = (rvfi_csr_wmask_q);
1488+
end
1489+
1490+
`define RVFI_CONNECT(CSR_ADDR, CSR_NAME, CSR_RDATA, CSR_WDATA, CSR_RMASK, CSR_WMASK) \
1491+
bit [63:0] rvfi_``CSR_NAME``_csr_rdata;\
1492+
bit [63:0] rvfi_``CSR_NAME``_csr_wdata;\
1493+
bit [63:0] rvfi_``CSR_NAME``_csr_rmask;\
1494+
bit [63:0] rvfi_``CSR_NAME``_csr_wmask;\
1495+
wire [63:0] rvfi_``CSR_NAME``_csr_wmask_q; \
1496+
wire [63:0] rvfi_``CSR_NAME``_csr_rmask_q; \
1497+
assign rvfi_csr_if.rvfi_named_csr_rdata[CSR_ADDR] = (!rvfi_csr_bypass) ? rvfi_``CSR_NAME``_csr_rdata : ``CSR_RDATA``; \
1498+
assign rvfi_csr_if.rvfi_named_csr_wdata[CSR_ADDR] = (!rvfi_csr_bypass) ? rvfi_``CSR_NAME``_csr_wdata : ``CSR_WDATA``; \
1499+
assign rvfi_csr_if.rvfi_named_csr_rmask[CSR_ADDR] = (!rvfi_csr_bypass) ? rvfi_``CSR_NAME``_csr_rmask : rvfi_``CSR_NAME``_csr_rmask_q; \
1500+
assign rvfi_csr_if.rvfi_named_csr_wmask[CSR_ADDR] = (!rvfi_csr_bypass) ? rvfi_``CSR_NAME``_csr_wmask : rvfi_``CSR_NAME``_csr_wmask_q; \
1501+
assign rvfi_``CSR_NAME``_csr_rmask_q = ((~csr_wr & csr_op_en_i & ~illegal_csr_insn_o & (csr_addr_i == CSR_ADDR)) CSR_RMASK) ? -1 : 0; \
1502+
assign rvfi_``CSR_NAME``_csr_wmask_q = ((csr_wr & csr_op_en_i & ~illegal_csr_insn_o & (csr_addr_i == CSR_ADDR)) CSR_WMASK) ? -1 : 0; \
1503+
always @(posedge clknrst_if.clk) begin \
1504+
rvfi_``CSR_NAME``_csr_rdata = ``CSR_RDATA``; \
1505+
rvfi_``CSR_NAME``_csr_wdata = ``CSR_WDATA``; \
1506+
rvfi_``CSR_NAME``_csr_rmask = (rvfi_``CSR_NAME``_csr_rmask_q); \
1507+
rvfi_``CSR_NAME``_csr_wmask = (rvfi_``CSR_NAME``_csr_wmask_q); \
1508+
end
1509+
1510+
`RVFI_CONNECT( CSR_MSTATUS, mstatus , mstatus_extended_read , mstatus_extended_write , , || mstatus_en)
1511+
`RVFI_CONNECT( CSR_MIE, mie , mie_q , mie_d , , || mie_en )
1512+
`RVFI_CONNECT( CSR_MIP, mip , mip , csr_wdata_i , , )
1513+
`RVFI_CONNECT( CSR_MISA, misa , MISA_VALUE , csr_wdata_i , , )
1514+
`RVFI_CONNECT( CSR_MTVEC, mtvec , mtvec_q , mtvec_d , , || mtvec_en )
1515+
`RVFI_CONNECT( CSR_MEPC, mepc , mepc_q , mepc_d , , || mepc_en )
1516+
`RVFI_CONNECT( CSR_MCAUSE, mcause , mcause_q , mcause_d , , || mcause_en )
1517+
`RVFI_CONNECT( CSR_MTVAL, mtval , mtval_q , mtval_d , , || mtval_en )
1518+
`RVFI_CONNECT( CSR_MSTATUSH, mstatush , 'h0 , csr_wdata_i , , )
1519+
`RVFI_CONNECT( CSR_DCSR, dcsr , dcsr_q , dcsr_d , , || dcsr_en)
1520+
`RVFI_CONNECT( CSR_DPC, dpc , depc_q , depc_d , , || depc_en)
1521+
`RVFI_CONNECT( CSR_DSCRATCH0, dscratch0 , dscratch0_q , csr_wdata_i , , || dscratch0_en)
1522+
`RVFI_CONNECT( CSR_DSCRATCH1, dscratch1 , dscratch1_q , csr_wdata_i , , || dscratch1_en)
1523+
1524+
`endif
14481525

14491526
////////////////
14501527
// Assertions //

‎rtl/cve2_pkg.sv

+80
Original file line numberDiff line numberDiff line change
@@ -574,5 +574,85 @@ package cve2_pkg;
574574
// alter this to point to their system specific configuration data structure.
575575
localparam logic [31:0] CSR_MCONFIGPTR_VALUE = 32'b0;
576576

577+
// RVFI CSR element
578+
typedef struct packed {
579+
bit [63:0] rdata;
580+
bit [63:0] rmask;
581+
bit [63:0] wdata;
582+
bit [63:0] wmask;
583+
} rvfi_csr_elmt_t;
584+
585+
// RVFI CSR structure
586+
typedef struct packed {
587+
rvfi_csr_elmt_t fflags;
588+
rvfi_csr_elmt_t frm;
589+
rvfi_csr_elmt_t fcsr;
590+
rvfi_csr_elmt_t ftran;
591+
rvfi_csr_elmt_t dcsr;
592+
rvfi_csr_elmt_t dpc;
593+
rvfi_csr_elmt_t dscratch0;
594+
rvfi_csr_elmt_t dscratch1;
595+
rvfi_csr_elmt_t sstatus;
596+
rvfi_csr_elmt_t sie;
597+
rvfi_csr_elmt_t sip;
598+
rvfi_csr_elmt_t stvec;
599+
rvfi_csr_elmt_t scounteren;
600+
rvfi_csr_elmt_t sscratch;
601+
rvfi_csr_elmt_t sepc;
602+
rvfi_csr_elmt_t scause;
603+
rvfi_csr_elmt_t stval;
604+
rvfi_csr_elmt_t satp;
605+
rvfi_csr_elmt_t mstatus;
606+
rvfi_csr_elmt_t mstatush;
607+
rvfi_csr_elmt_t misa;
608+
rvfi_csr_elmt_t medeleg;
609+
rvfi_csr_elmt_t mideleg;
610+
rvfi_csr_elmt_t mie;
611+
rvfi_csr_elmt_t mtvec;
612+
rvfi_csr_elmt_t mcounteren;
613+
rvfi_csr_elmt_t mscratch;
614+
rvfi_csr_elmt_t mepc;
615+
rvfi_csr_elmt_t mcause;
616+
rvfi_csr_elmt_t mtval;
617+
rvfi_csr_elmt_t mip;
618+
rvfi_csr_elmt_t menvcfg;
619+
rvfi_csr_elmt_t menvcfgh;
620+
rvfi_csr_elmt_t mvendorid;
621+
rvfi_csr_elmt_t marchid;
622+
rvfi_csr_elmt_t mhartid;
623+
rvfi_csr_elmt_t mcountinhibit;
624+
rvfi_csr_elmt_t mcycle;
625+
rvfi_csr_elmt_t mcycleh;
626+
rvfi_csr_elmt_t minstret;
627+
rvfi_csr_elmt_t minstreth;
628+
rvfi_csr_elmt_t cycle;
629+
rvfi_csr_elmt_t cycleh;
630+
rvfi_csr_elmt_t instret;
631+
rvfi_csr_elmt_t instreth;
632+
rvfi_csr_elmt_t dcache;
633+
rvfi_csr_elmt_t icache;
634+
rvfi_csr_elmt_t acc_cons;
635+
rvfi_csr_elmt_t pmpcfg0;
636+
rvfi_csr_elmt_t pmpcfg1;
637+
rvfi_csr_elmt_t pmpcfg2;
638+
rvfi_csr_elmt_t pmpcfg3;
639+
rvfi_csr_elmt_t pmpaddr0;
640+
rvfi_csr_elmt_t pmpaddr1;
641+
rvfi_csr_elmt_t pmpaddr2;
642+
rvfi_csr_elmt_t pmpaddr3;
643+
rvfi_csr_elmt_t pmpaddr4;
644+
rvfi_csr_elmt_t pmpaddr5;
645+
rvfi_csr_elmt_t pmpaddr6;
646+
rvfi_csr_elmt_t pmpaddr7;
647+
rvfi_csr_elmt_t pmpaddr8;
648+
rvfi_csr_elmt_t pmpaddr9;
649+
rvfi_csr_elmt_t pmpaddr10;
650+
rvfi_csr_elmt_t pmpaddr11;
651+
rvfi_csr_elmt_t pmpaddr12;
652+
rvfi_csr_elmt_t pmpaddr13;
653+
rvfi_csr_elmt_t pmpaddr14;
654+
rvfi_csr_elmt_t pmpaddr15;
655+
} rvfi_csr_t;
656+
577657
endpackage
578658

‎rtl/cve2_top_tracing.sv

-2
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,6 @@ module cve2_top_tracing import cve2_pkg::*; #(
1111
parameter int unsigned MHPMCounterWidth = 40,
1212
parameter bit RV32E = 1'b0,
1313
parameter rv32m_e RV32M = RV32MFast,
14-
parameter bit BranchPredictor = 1'b0,
1514
parameter int unsigned DmHaltAddr = 32'h1A110800,
1615
parameter int unsigned DmExceptionAddr = 32'h1A110808
1716
) (
@@ -112,7 +111,6 @@ module cve2_top_tracing import cve2_pkg::*; #(
112111
.MHPMCounterWidth ( MHPMCounterWidth ),
113112
.RV32E ( RV32E ),
114113
.RV32M ( RV32M ),
115-
.BranchPredictor ( BranchPredictor ),
116114
.DmHaltAddr ( DmHaltAddr ),
117115
.DmExceptionAddr ( DmExceptionAddr )
118116
) u_cve2_top (

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