From 28f64b9b5608990317f5670394d22358749eae05 Mon Sep 17 00:00:00 2001 From: Olaf Seibert Date: Wed, 19 Jul 2023 20:23:45 +0200 Subject: [PATCH] Add pseudo registers MODEL and PORT to RQ and TQ controllers. EXAMINE RQ MODEL DEPOSIT RQ MODEL 42 EXAMINE RQ STATE --- PDP11/pdp11_rq.c | 31 ++++++++++++++++++++++++------- PDP11/pdp11_tq.c | 22 +++++++++++++++++----- 2 files changed, 41 insertions(+), 12 deletions(-) diff --git a/PDP11/pdp11_rq.c b/PDP11/pdp11_rq.c index e1a4dfef6..4a3bbc678 100644 --- a/PDP11/pdp11_rq.c +++ b/PDP11/pdp11_rq.c @@ -757,7 +757,7 @@ x RA73 70(+1) 21 2667+ 21 1 ? 3920490 #define KLESI_MODEL 3 #define RUX50_CTYPE 2 // UNIBUS RX50-only controller -#define RUX50_UQPM 10 // this should be 10 according to the MSCP spec +#define RUX50_UQPM 10 #define RUX50_MODEL 10 #define UDA50_CTYPE 3 // UNIBUS SDI (RAxx) controller @@ -781,7 +781,7 @@ x RA73 70(+1) 21 2667+ 21 1 ? 3920490 #define KRQ50_MODEL 16 #define KRU50_CTYPE 8 // UNIBUS RRD40/50 CDROM controller -#define KRU50_UQPM 26 // unassigned in appendix C +#define KRU50_UQPM 26 #define KRU50_MODEL 26 struct drvtyp { @@ -920,6 +920,8 @@ typedef struct { uint32 hat; /* host timer */ uint32 htmo; /* host timeout */ uint32 ctype; /* controller type */ + uint16 mscp_model; /* mscp ctrlr model number */ + uint16 mscp_uqpm; /* mscp port model number */ struct uq_ring cq; /* cmd ring */ struct uq_ring rq; /* rsp ring */ struct rqpkt pak[RQ_NPKTS]; /* packet queue */ @@ -1093,6 +1095,8 @@ REG rq_reg[] = { { FLDATA (PRGI, rq_ctx.prgi, 0), REG_HIDDEN }, { FLDATA (PIP, rq_ctx.pip, 0), REG_HIDDEN }, { BINRDATA(CTYPE, rq_ctx.ctype, 32), REG_HIDDEN }, + { DRDATAD (MODEL, rq_ctx.mscp_model, 16, "mscp controller model id") }, + { DRDATAD (PORT, rq_ctx.mscp_uqpm, 16, "mscp port model id") }, { DRDATAD (ITIME, rq_itime, 24, "init time delay, except stage 4"), PV_LEFT + REG_NZ }, { DRDATAD (I4TIME, rq_itime4, 24, "init stage 4 delay"), PV_LEFT + REG_NZ }, { DRDATAD (QTIME, rq_qtime, 24, "response time for 'immediate' packets"), PV_LEFT + REG_NZ }, @@ -1290,6 +1294,8 @@ REG rqb_reg[] = { { FLDATA (PRGI, rqb_ctx.prgi, 0), REG_HIDDEN }, { FLDATA (PIP, rqb_ctx.pip, 0), REG_HIDDEN }, { BINRDATA(CTYPE, rqb_ctx.ctype, 32), REG_HIDDEN }, + { DRDATAD (MODEL, rqb_ctx.mscp_model, 16, "mscp controller model id") }, + { DRDATAD (PORT, rqb_ctx.mscp_uqpm, 16, "mscp port model id") }, { VBRDATAD (PKTS, rqb_ctx.pak, DEV_RDX, 16, sizeof(rq_ctx.pak)/2, "packet buffers, 33W each, 32 entries") }, { URDATAD (CPKT, rqb_unit[0].cpkt, 10, 5, 0, RQ_NUMDR, 0, "current packet, units 0 to 3") }, { URDATAD (UCNUM, rqb_unit[0].cnum, 10, 5, 0, RQ_NUMDR, 0, "ctrl number, units 0 to 3") }, @@ -1363,6 +1369,8 @@ REG rqc_reg[] = { { FLDATA (PRGI, rqc_ctx.prgi, 0), REG_HIDDEN }, { FLDATA (PIP, rqc_ctx.pip, 0), REG_HIDDEN }, { BINRDATA(CTYPE, rqc_ctx.ctype, 32), REG_HIDDEN }, + { DRDATAD (MODEL, rqc_ctx.mscp_model, 16, "mscp controller model id") }, + { DRDATAD (PORT, rqc_ctx.mscp_uqpm, 16, "mscp port model id") }, { VBRDATAD (PKTS, rqc_ctx.pak, DEV_RDX, 16, sizeof(rq_ctx.pak)/2, "packet buffers, 33W each, 32 entries") }, { URDATAD (CPKT, rqc_unit[0].cpkt, 10, 5, 0, RQ_NUMDR, 0, "current packet, units 0 to 3") }, { URDATAD (UCNUM, rqc_unit[0].cnum, 10, 5, 0, RQ_NUMDR, 0, "ctrl number, units 0 to 3") }, @@ -1436,6 +1444,8 @@ REG rqd_reg[] = { { FLDATA (PRGI, rqd_ctx.prgi, 0), REG_HIDDEN }, { FLDATA (PIP, rqd_ctx.pip, 0), REG_HIDDEN }, { BINRDATA(CTYPE, rqd_ctx.ctype, 32), REG_HIDDEN }, + { DRDATAD (MODEL, rqd_ctx.mscp_model, 16, "mscp controller model id") }, + { DRDATAD (PORT, rqd_ctx.mscp_uqpm, 16, "mscp port model id") }, { VBRDATAD (PKTS, rqd_ctx.pak, DEV_RDX, 16, sizeof(rq_ctx.pak)/2, "packet buffers, 33W each, 32 entries") }, { URDATAD (CPKT, rqd_unit[0].cpkt, 10, 5, 0, RQ_NUMDR, 0, "current packet, units 0 to 3") }, { URDATAD (UCNUM, rqd_unit[0].cnum, 10, 5, 0, RQ_NUMDR, 0, "ctrl number, units 0 to 3") }, @@ -1581,7 +1591,7 @@ for (i = 0; i < (lnt >> 1); i++) /* clr buffer */ if (Map_WriteW (base, lnt, zero)) /* zero comm area */ return rq_fatal (cp, PE_QWE); /* error? */ cp->sa = SA_S4 | /* send step 4 */ - (ctlr_tab[cp->ctype].uqpm << SA_S4C_V_MOD) | + (cp->mscp_uqpm << SA_S4C_V_MOD) | (RQ_SVER << SA_S4C_V_VER); cp->csta = CST_S4; /* set step 4 */ rq_init_int (cp); /* poke host */ @@ -2013,7 +2023,7 @@ else { cp->pak[pkt].d[SCC_CIDB] = 0; cp->pak[pkt].d[SCC_CIDC] = 0; cp->pak[pkt].d[SCC_CIDD] = (RQ_CLASS << SCC_CIDD_V_CLS) | - (ctlr_tab[cp->ctype].model << SCC_CIDD_V_MOD); + (cp->mscp_model << SCC_CIDD_V_MOD); cp->pak[pkt].d[SCC_MBCL] = 0; /* max bc */ cp->pak[pkt].d[SCC_MBCH] = 0; } @@ -2481,7 +2491,7 @@ cp->pak[pkt].d[DTE_CIDA] = 0; /* ctrl ID */ cp->pak[pkt].d[DTE_CIDB] = 0; cp->pak[pkt].d[DTE_CIDC] = 0; cp->pak[pkt].d[DTE_CIDD] = (RQ_CLASS << DTE_CIDD_V_CLS) | - (ctlr_tab[cp->ctype].model << DTE_CIDD_V_MOD); + (cp->mscp_model << DTE_CIDD_V_MOD); cp->pak[pkt].d[DTE_VER] = (RQ_HVER << DTE_VER_V_HVER) | (RQ_SVER << DTE_VER_V_SVER); cp->pak[pkt].d[DTE_MLUN] = lu; /* MLUN */ @@ -2523,7 +2533,7 @@ cp->pak[pkt].d[HBE_CIDA] = 0; /* ctrl ID */ cp->pak[pkt].d[HBE_CIDB] = 0; cp->pak[pkt].d[HBE_CIDC] = 0; cp->pak[pkt].d[HBE_CIDD] = (RQ_CLASS << DTE_CIDD_V_CLS) | - (ctlr_tab[cp->ctype].model << DTE_CIDD_V_MOD); + (cp->mscp_model << DTE_CIDD_V_MOD); cp->pak[pkt].d[HBE_VER] = (RQ_HVER << HBE_VER_V_HVER) | /* versions */ (RQ_SVER << HBE_VER_V_SVER); cp->pak[pkt].d[HBE_RSV] = 0; @@ -2551,7 +2561,7 @@ cp->pak[pkt].d[PLF_CIDA] = 0; /* cntl ID */ cp->pak[pkt].d[PLF_CIDB] = 0; cp->pak[pkt].d[PLF_CIDC] = 0; cp->pak[pkt].d[PLF_CIDD] = (RQ_CLASS << PLF_CIDD_V_CLS) | - (ctlr_tab[cp->ctype].model << PLF_CIDD_V_MOD); + (cp->mscp_model << DTE_CIDD_V_MOD); cp->pak[pkt].d[PLF_VER] = (RQ_SVER << PLF_VER_V_SVER) | (RQ_HVER << PLF_VER_V_HVER); cp->pak[pkt].d[PLF_ERR] = err; @@ -3037,6 +3047,8 @@ MSC *cp = rq_ctxmap[uptr->cnum]; if (val < 0) return SCPE_ARG; cp->ctype = val; +cp->mscp_model = ctlr_tab[cp->ctype].model; +cp->mscp_uqpm = ctlr_tab[cp->ctype].uqpm; return SCPE_OK; } @@ -3109,6 +3121,11 @@ cp->cnum = cidx; /* init index */ if (cp->ctype == DEFAULT_CTYPE) cp->ctype = (UNIBUS ? UDA50_CTYPE : MICROVAX1 ? RQDX1_CTYPE : RQDX3_CTYPE); +if (cp->mscp_model == 0) { + cp->mscp_model = ctlr_tab[cp->ctype].model; + cp->mscp_uqpm = ctlr_tab[cp->ctype].uqpm; + fprintf(stderr, "setting rq model and uqpm at reset\r\n"); + } if (!plugs_inited ) { #if !defined (VM_VAX) diff --git a/PDP11/pdp11_tq.c b/PDP11/pdp11_tq.c index e8ebdfe81..e29b50d74 100644 --- a/PDP11/pdp11_tq.c +++ b/PDP11/pdp11_tq.c @@ -270,6 +270,8 @@ int32 tq_qtime = 200; /* queue time */ int32 tq_xtime = 500; /* transfer time */ int32 tq_rwtime = 2000000; /* rewind time 2 sec (adjusted later) */ int32 tq_typ = INIT_TYPE; /* device type */ +int16 tq_mscp_model; /* mscp ctrlr model number */ +int16 tq_mscp_uqpm; /* mscp port model number */ /* Command table - legal modifiers (low 16b) and flags (high 16b) */ @@ -468,6 +470,8 @@ REG tq_reg[] = { { VBRDATAD (PKTS, tq_pkt, DEV_RDX, 16, TQ_NPKTS * (TQ_PKT_SIZE_W + 1), "packet buffers, 33W each, 32 entries") }, { URDATAD (PLUG, tq_unit[0].unit_plug, 10, 32, 0, TQ_NUMDR, PV_LEFT | REG_RO, "unit plug value, units 0 to 3") }, { DRDATA (DEVTYPE, tq_typ, 2), REG_HRO }, + { DRDATAD (MODEL, tq_mscp_model,16, "mscp controller model id") }, + { DRDATAD (PORT, tq_mscp_uqpm,16, "mscp port model id") }, { DRDATA (DEVCAP, drv_tab[TQU_TYPE].cap, T_ADDR_W), PV_LEFT | REG_HRO }, { GRDATA (DEVADDR, tq_dib.ba, DEV_RDX, 32, 0), REG_HRO }, { GRDATA (DEVVEC, tq_dib.vec, DEV_RDX, 16, 0), REG_HRO }, @@ -644,7 +648,7 @@ for (i = 0; i < (lnt >> 1); i++) /* clr buffer */ zero[i] = 0; if (Map_WriteW (base, lnt, zero)) /* zero comm area */ return tq_fatal (PE_QWE); /* error? */ -tq_sa = SA_S4 | (drv_tab[tq_typ].uqpm << SA_S4C_V_MOD) |/* send step 4 */ +tq_sa = SA_S4 | (tq_mscp_uqpm << SA_S4C_V_MOD) | /* send step 4 */ ((drv_tab[tq_typ].cver & 0xFF) << SA_S4C_V_VER); tq_csta = CST_S4; /* set step 4 */ tq_init_int (); /* poke host */ @@ -1093,7 +1097,7 @@ else { tq_pkt[pkt].d[SCC_CIDB] = 0; tq_pkt[pkt].d[SCC_CIDC] = 0; tq_pkt[pkt].d[SCC_CIDD] = (TQ_CLASS << SCC_CIDD_V_CLS) | - (drv_tab[tq_typ].cmod << SCC_CIDD_V_MOD); + (tq_mscp_model << SCC_CIDD_V_MOD); PUTP32 (pkt, SCC_MBCL, TQ_MAXFR); /* max bc */ tq_putr (pkt, OP_SCC | OP_END, 0, ST_SUC, SCC_LNT, UQ_TYP_SEQ); } @@ -1668,7 +1672,7 @@ tq_pkt[pkt].d[DTE_CIDA] = 0; /* ctrl ID */ tq_pkt[pkt].d[DTE_CIDB] = 0; tq_pkt[pkt].d[DTE_CIDC] = 0; tq_pkt[pkt].d[DTE_CIDD] = (TQ_CLASS << DTE_CIDD_V_CLS) | - (drv_tab[tq_typ].cmod << DTE_CIDD_V_MOD); + (tq_mscp_model << DTE_CIDD_V_MOD); tq_pkt[pkt].d[DTE_VER] = drv_tab[tq_typ].cver; /* ctrl ver */ tq_pkt[pkt].d[DTE_MLUN] = lu; /* MLUN */ tq_pkt[pkt].d[DTE_UIDA] = lu; /* unit ID */ @@ -1702,7 +1706,7 @@ tq_pkt[pkt].d[HBE_CIDA] = 0; /* ctrl ID */ tq_pkt[pkt].d[HBE_CIDB] = 0; tq_pkt[pkt].d[HBE_CIDC] = 0; tq_pkt[pkt].d[DTE_CIDD] = (TQ_CLASS << DTE_CIDD_V_CLS) | - (drv_tab[tq_typ].cmod << DTE_CIDD_V_MOD); + (tq_mscp_model << DTE_CIDD_V_MOD); tq_pkt[pkt].d[HBE_VER] = drv_tab[tq_typ].cver; /* ctrl ver */ tq_pkt[pkt].d[HBE_RSV] = 0; PUTP32 (pkt, HBE_BADL, ba); /* bad addr */ @@ -1724,7 +1728,7 @@ tq_pkt[pkt].d[PLF_CIDA] = 0; /* cntl ID */ tq_pkt[pkt].d[PLF_CIDB] = 0; tq_pkt[pkt].d[PLF_CIDC] = 0; tq_pkt[pkt].d[PLF_CIDD] = (TQ_CLASS << PLF_CIDD_V_CLS) | - (drv_tab[tq_typ].cmod << PLF_CIDD_V_MOD); + (tq_mscp_model << PLF_CIDD_V_MOD); tq_pkt[pkt].d[PLF_VER] = drv_tab[tq_typ].cver; tq_pkt[pkt].d[PLF_ERR] = (uint16)err; tq_putr (pkt, FM_CNT, LF_SNR, ST_CNT, PLF_LNT, UQ_TYP_DAT); @@ -2077,6 +2081,12 @@ int32 i, j; UNIT *uptr; static t_bool plugs_inited = FALSE; +if (tq_mscp_model == 0) { + tq_mscp_model = drv_tab[tq_typ].cmod; + tq_mscp_uqpm = drv_tab[tq_typ].uqpm; + fprintf(stderr, "setting tq model and uqpm at reset\r\n"); + } + for (i=tq_max_plug=0; iunits[i].unit_plug > tq_max_plug) tq_max_plug = (uint16)dptr->units[i].unit_plug; @@ -2410,6 +2420,8 @@ if (cptr) { drv_tab[TQU_TYPE].cap = ((t_addr) cap) << 20; } tq_typ = val; +tq_mscp_model = drv_tab[tq_typ].cmod; +tq_mscp_uqpm = drv_tab[tq_typ].uqpm; for (i = 0; i < TQ_NUMDR; i++) tq_unit[i].capac = drv_tab[tq_typ].cap; return SCPE_OK;