@@ -138,11 +138,10 @@ associated with the source address of the indirect branch. Specifically,
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the BHB might be shared across privilege levels even in the presence of
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Enhanced IBRS.
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- Currently the only known real-world BHB attack vector is via
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- unprivileged eBPF. Therefore, it's highly recommended to not enable
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- unprivileged eBPF, especially when eIBRS is used (without retpolines).
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- For a full mitigation against BHB attacks, it's recommended to use
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- retpolines (or eIBRS combined with retpolines).
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+ Previously the only known real-world BHB attack vector was via unprivileged
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+ eBPF. Further research has found attacks that don't require unprivileged eBPF.
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+ For a full mitigation against BHB attacks it is recommended to set BHI_DIS_S or
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+ use the BHB clearing sequence.
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Attack scenarios
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----------------
@@ -430,6 +429,23 @@ The possible values in this file are:
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'PBRSB-eIBRS: Not affected' CPU is not affected by PBRSB
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=========================== =======================================================
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+ - Branch History Injection (BHI) protection status:
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+
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+ .. list-table ::
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+
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+ * - BHI: Not affected
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+ - System is not affected
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+ * - BHI: Retpoline
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+ - System is protected by retpoline
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+ * - BHI: BHI_DIS_S
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+ - System is protected by BHI_DIS_S
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+ * - BHI: SW loop, KVM SW loop
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+ - System is protected by software clearing sequence
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+ * - BHI: Vulnerable
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+ - System is vulnerable to BHI
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+ * - BHI: Vulnerable, KVM: SW loop
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+ - System is vulnerable; KVM is protected by software clearing sequence
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+
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Full mitigation might require a microcode update from the CPU
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vendor. When the necessary microcode is not available, the kernel will
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report vulnerability.
@@ -484,11 +500,18 @@ Spectre variant 2
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Systems which support enhanced IBRS (eIBRS) enable IBRS protection once at
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boot, by setting the IBRS bit, and they're automatically protected against
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- Spectre v2 variant attacks, including cross-thread branch target injections
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- on SMT systems (STIBP). In other words, eIBRS enables STIBP too.
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+ some Spectre v2 variant attacks. The BHB can still influence the choice of
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+ indirect branch predictor entry, and although branch predictor entries are
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+ isolated between modes when eIBRS is enabled, the BHB itself is not isolated
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+ between modes. Systems which support BHI_DIS_S will set it to protect against
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+ BHI attacks.
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- Legacy IBRS systems clear the IBRS bit on exit to userspace and
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- therefore explicitly enable STIBP for that
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+ On Intel's enhanced IBRS systems, this includes cross-thread branch target
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+ injections on SMT systems (STIBP). In other words, Intel eIBRS enables
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+ STIBP, too.
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+
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+ AMD Automatic IBRS does not protect userspace, and Legacy IBRS systems clear
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+ the IBRS bit on exit to userspace, therefore both explicitly enable STIBP.
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The retpoline mitigation is turned on by default on vulnerable
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CPUs. It can be forced on or off by the administrator
@@ -622,9 +645,10 @@ kernel command line.
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retpoline,generic Retpolines
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retpoline,lfence LFENCE; indirect branch
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retpoline,amd alias for retpoline,lfence
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- eibrs enhanced IBRS
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- eibrs,retpoline enhanced IBRS + Retpolines
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- eibrs,lfence enhanced IBRS + LFENCE
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+ eibrs Enhanced/Auto IBRS
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+ eibrs,retpoline Enhanced/Auto IBRS + Retpolines
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+ eibrs,lfence Enhanced/Auto IBRS + LFENCE
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+ ibrs use IBRS to protect kernel
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Not specifying this option is equivalent to
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spectre_v2=auto.
@@ -684,6 +708,20 @@ For user space mitigation:
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spectre_v2=off. Spectre variant 1 mitigations
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cannot be disabled.
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+ spectre_bhi=
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+
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+ [X86] Control mitigation of Branch History Injection
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+ (BHI) vulnerability. This setting affects the deployment
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+ of the HW BHI control and the SW BHB clearing sequence.
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+
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+ on
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+ (default) Enable the HW or SW mitigation as
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+ needed.
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+ off
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+ Disable the mitigation.
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+
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+ For spectre_v2_user see Documentation/admin-guide/kernel-parameters.txt
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+
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Mitigation selection guide
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--------------------------
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