allow specifying the address for reg_rd and reg_wr in 32-bit words

This change allows specifying the address in 32-bit words (i.e. the
address as seen from the ULP), in addition to the existing mode of
specifying a register's full address on the DPORT bus.

If an address is between 0 and 0x3ff, treat it as a word offset (ULP
address), otherwise treat it as a full address on the DPORT bus
as before.

Author: wnienhaus

esp32_ulp/opcodes.py

@@ -356,7 +356,9 @@ def get_cond(arg):
 def _soc_reg_to_ulp_periph_sel(reg):
     # Map SoC peripheral register to periph_sel field of RD_REG and WR_REG instructions.
     ret = 3
-    if reg < DR_REG_RTCCNTL_BASE:
+    if reg < 0x3ff:
+        ret = 0
+    elif reg < DR_REG_RTCCNTL_BASE:
         raise ValueError("invalid register base")
     elif reg < DR_REG_RTCIO_BASE:
         ret = RD_REG_PERIPH_RTC_CNTL
@@ -373,7 +375,10 @@ def _soc_reg_to_ulp_periph_sel(reg):
 
 def i_reg_wr(reg, high_bit, low_bit, val):
     reg = get_imm(reg)
-    _wr_reg.addr = (reg & 0xff) >> 2
+    if reg < 0x3ff:  # see https://github.com/espressif/binutils-esp32ulp/blob/master/gas/config/tc-esp32ulp_esp32.c
+        _wr_reg.addr = reg
+    else:
+        _wr_reg.addr = (reg & 0xff) >> 2
     _wr_reg.periph_sel = _soc_reg_to_ulp_periph_sel(reg)
     _wr_reg.data = get_imm(val)
     _wr_reg.low = get_imm(low_bit)
@@ -384,7 +389,10 @@ def i_reg_wr(reg, high_bit, low_bit, val):
 
 def i_reg_rd(reg, high_bit, low_bit):
     reg = get_imm(reg)
-    _rd_reg.addr = (reg & 0xff) >> 2
+    if reg < 0x3ff: # see https://github.com/espressif/binutils-esp32ulp/blob/master/gas/config/tc-esp32ulp_esp32.c
+        _rd_reg.addr = reg
+    else:
+        _rd_reg.addr = (reg & 0xff) >> 2
     _rd_reg.periph_sel = _soc_reg_to_ulp_periph_sel(reg)
     _rd_reg.unused = 0
     _rd_reg.low = get_imm(low_bit)

tests/compat/fixes.S

@@ -17,4 +17,9 @@ counter:
 entry:
   MOVE R1, gpio
   WAIT 42
+
+  # reg_rd/reg_wr with "short" and "long" address notation
+  reg_rd 12, 7, 0
+  reg_rd 0x3ff48000, 7, 0
+
   halt