@@ -19,6 +19,9 @@ Assume first the system has the power states described [above](theory_of_operati
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7 . Set and poll [ ` CFG_CDC_SYNC ` ] ( registers.md#cfg_cdc_sync ) to ensure above settings propagate across clock domains.
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8 . Execute wait-for-interrupt instruction on the processing host.
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+ Note that entering low power mode requires that pwrmgr's ` pwr_cpu_i.core_sleeping ` input be at logic high long enough to be sampled.
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+ A wait-for-interrupt instruction does not guarantee entry into low power, since the CPU could immediately resume execution in some cases.
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### Possible Exits
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Once low power is initiated, the system may exit due to several reasons.
@@ -30,6 +33,18 @@ Once low power is initiated, the system may exit due to several reasons.
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In both fall through exit and aborted entry, the power manager does not actually enter low power.
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Instead the low power entry is interrupted and the system restored to active state.
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+ In addition, a CPU's sleeping signal that is too short for the power manager to sample will not trigger even an attempt to go to low power.
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+ In such cases, there will be no bits set in [ ` WAKE_INFO ` ] ( registers.md#wake_info ) , and no side effects of pwrmgr entering low power mode will trigger.
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+ To check the exit condition, software can follow these steps:
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+ 1 . Clear low power hint in [ ` CONTROL ` ] ( registers.md#control ) and poll until it becomes cleared.
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+ <!-- As of this writing, the CONTROL REGWEN locks out writes to CONTROL once pwrmgr receives the trigger to enable low power mode.
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+ pwrmgr enables writes again upon exiting low power mode.
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+ For the case where low power isn't even *attempted* due to short WFI, CONTROL will not be locked, so the clear will succeed. -->
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+ - Until the hint clears, the values in [ ` WAKE_INFO ` ] ( registers.md#wake_info ) may not reflect the true exit condition.
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+ 2 . Check [ ` WAKE_INFO ` ] ( registers.md#wake_info ) to get the condition.
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+ - If no bits are set, then this was a fast fall through, where low power entry was not attempted.
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+
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## Programmer Sequence for Exiting Low Power
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There are two separate cases for low power exit.
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