Merge branch 'lowRISC:earlgrey_1.0.0' into earlgrey_1.0.0

Author: tommychiu-github

.github/workflows/ci.yml

@@ -713,3 +713,19 @@ jobs:
       - name: Check for unrunnable tests
         run: ./ci/scripts/check-unrunnable-tests.sh
         continue-on-error: true
+
+  qemu_smoketest:
+    name: QEMU smoketest
+    runs-on: ubuntu-22.04-vivado
+    needs: quick_lint
+    steps:
+      - uses: actions/checkout@v4
+        with:
+          fetch-depth: 0
+      - name: Prepare environment
+        uses: ./.github/actions/prepare-env
+        with:
+          service_account_json: '${{ secrets.BAZEL_CACHE_CREDS }}'
+      - name: Execute QEMU smoketest
+        run: |
+          ./bazelisk.sh test //sw/device/tests:rom_exit_immediately_sim_qemu_base

WORKSPACE

@@ -153,6 +153,9 @@ bitstreams_repo(name = "bitstreams")
 load("//third_party/open-dice:repos.bzl", "open_dice_repos")
 open_dice_repos()
 
+load("//third_party/qemu:repos.bzl", "qemu_opentitan_repos")
+qemu_opentitan_repos()
+
 # Setup for linking in externally managed test and provisioning customizations
 # for both secure/non-secure manufacturer domains.
 load("//rules:hooks_setup.bzl", "hooks_setup", "provisioning_exts_setup", "secure_hooks_setup")

ci/scripts/build-bitstream-vivado.sh

@@ -106,7 +106,4 @@ BITSTREAM_FNAME="lowrisc_systems_chip_${FLAVOUR}_${TARGET}_0.1.bit"
 BITSTREAM_PATH="$OBJ_DIR/hw/synth-vivado/$BITSTREAM_FNAME"
 cp "$BITSTREAM_PATH" "$TOPLEVEL_BIN_DIR"
 
-cp "$OBJ_DIR/hw/synth-vivado/rom.mmi" "$TOPLEVEL_BIN_DIR"
-if [ $HAS_OTP == 1 ]; then
-    cp "$OBJ_DIR/hw/synth-vivado/otp.mmi" "$TOPLEVEL_BIN_DIR"
-fi
+cp "$OBJ_DIR/hw/synth-vivado/memories.mmi" "$TOPLEVEL_BIN_DIR"

doc/contributing/fpga/debugging_with_ila.md

@@ -237,7 +237,7 @@ The path to the synthesis log file is usually `bazel-out/k8-fastbuild/bin/hw/bit
 
 Once Vivado has successfully generated a bitstream, locate its directory with `dirname $(./bazelisk.sh outquery-all //hw/bitstream:rom --define bitstream=vivado)` (it will usually be `bazel-out/k8-fastbuild/bin/hw/bitstream/vivado`).
 Append `/build.fpga_cw310/synth-vivado` to that path.
-In the resulting directory, you should find `otp.mmi`, `rom.mmi`, and `lowrisc_systems_chip_earlgrey_cw310_0.1.bit`.
+In the resulting directory, you should find `memories.mmi` and `lowrisc_systems_chip_earlgrey_cw310_0.1.bit`.
 We will next copy those files into a local bitstream cache that Bazel can use.
 
 If you don't have a local bitstream cache yet, create one as follows:
@@ -254,7 +254,7 @@ mkdir -p $BAZEL_BITSTREAMS_CACHE/cache
 Create a directory with the name of the Git hash for which you have built the bitstream under `$BAZEL_BITSTREAMS_CACHE/cache/` (e.g,. `$BAZEL_BITSTREAMS_CACHE/cache/2e5a31b7d80b6eb97e114b2ca8f9e132ec7c83a6`).
 (You can find the relevant Git hash with `git log`, for example.
 If you have not committed the changes to implement the ILA yet, we recommend doing so at least locally.)
-Copy `otp.mmi` and `rom.mmi` to that directory.
+Copy `memories.mmi` to that directory.
 Copy `lowrisc_systems_chip_earlgrey_cw310_0.1.bit` also to that directory, then rename the copy to `lowrisc_systems_chip_earlgrey_cw310_0.1.bit.orig`.
 
 Now instruct Bazel to use a bitstream from the local cache by setting an `--offline` argument in the `BITSTREAM` environment variable; for example:

doc/contributing/fpga/ref_manual_fpga.md

@@ -143,8 +143,7 @@ The following files are produced as a result:
 * `fpga_cw310_rom.bit` (ROM, RMA OTP image)
 * `fpga_cw310_rom_otp_dev.bit` (ROM, DEV OTP image)
 * `lowrisc_systems_chip_earlgrey_cw310_0.1.bit` (test ROM, RMA OTP image)
-* `otp.mmi`
-* `rom.mmi`
+* `memories.mmi`
 
 If CI is working on the `master` branch, it puts selected build artifacts into a tarball, which it then uploads to the GCS bucket. The latest tarball is available here: https://storage.googleapis.com/opentitan-bitstreams/master/bitstream-latest.tar.gz
 

hw/bitstream/BUILD

@@ -70,25 +70,13 @@ filegroup(
 )
 
 filegroup(
-    name = "rom_mmi",
+    name = "cw310_mmi",
     testonly = True,
     srcs = select({
         "bitstream_skip": ["//hw/bitstream/universal:none"],
-        "bitstream_vivado": ["//hw/bitstream/vivado:rom_mmi"],
-        "bitstream_gcp_splice": ["@bitstreams//:chip_earlgrey_cw310_rom_mmi"],
-        "//conditions:default": ["@bitstreams//:chip_earlgrey_cw310_rom_mmi"],
-    }),
-    tags = ["manual"],
-)
-
-filegroup(
-    name = "otp_mmi",
-    testonly = True,
-    srcs = select({
-        "bitstream_skip": ["//hw/bitstream/universal:none"],
-        "bitstream_vivado": ["//hw/bitstream/vivado:otp_mmi"],
-        "bitstream_gcp_splice": ["@bitstreams//:chip_earlgrey_cw310_otp_mmi"],
-        "//conditions:default": ["@bitstreams//:chip_earlgrey_cw310_otp_mmi"],
+        "bitstream_vivado": ["//hw/bitstream/vivado:cw310_mmi"],
+        "bitstream_gcp_splice": ["@bitstreams//:chip_earlgrey_cw310_mmi"],
+        "//conditions:default": ["@bitstreams//:chip_earlgrey_cw310_mmi"],
     }),
     tags = ["manual"],
 )
@@ -99,7 +87,8 @@ bitstream_splice(
     testonly = True,
     src = ":bitstream",
     data = "//sw/device/lib/testing/test_rom:test_rom_fpga_cw310_scr_vmem",
-    meminfo = ":rom_mmi",
+    instance = "rom",
+    meminfo = ":cw310_mmi",
     tags = ["manual"],
     update_usr_access = True,
 )
@@ -109,7 +98,8 @@ bitstream_splice(
     testonly = True,
     src = ":bitstream",
     data = "//sw/device/silicon_creator/rom:mask_rom_fpga_cw310_scr_vmem",
-    meminfo = ":rom_mmi",
+    instance = "rom",
+    meminfo = ":cw310_mmi",
     tags = ["manual"],
     update_usr_access = True,
 )
@@ -121,7 +111,8 @@ bitstream_splice(
         testonly = True,
         src = ":mask_rom",
         data = img_target,
-        meminfo = ":otp_mmi",
+        instance = "otp",
+        meminfo = ":cw310_mmi",
         tags = ["manual"],
         update_usr_access = True,
     )
@@ -133,8 +124,7 @@ bitstream_fragment_from_manifest(
     name = "chip_earlgrey_cw310_cached_fragment",
     srcs = [
         "@bitstreams//:chip_earlgrey_cw310_bitstream",
-        "@bitstreams//:chip_earlgrey_cw310_otp_mmi",
-        "@bitstreams//:chip_earlgrey_cw310_rom_mmi",
+        "@bitstreams//:chip_earlgrey_cw310_mmi",
     ],
     design = "chip_earlgrey_cw310",
     manifest = "@bitstreams//:manifest",
@@ -155,8 +145,7 @@ bitstream_fragment_from_manifest(
     name = "chip_earlgrey_cw310_hyperdebug_cached_fragment",
     srcs = [
         "@bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream",
-        "@bitstreams//:chip_earlgrey_cw310_hyperdebug_otp_mmi",
-        "@bitstreams//:chip_earlgrey_cw310_hyperdebug_rom_mmi",
+        "@bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi",
     ],
     design = "chip_earlgrey_cw310_hyperdebug",
     manifest = "@bitstreams//:manifest",
@@ -177,8 +166,7 @@ bitstream_fragment_from_manifest(
     name = "chip_earlgrey_cw340_cached_fragment",
     srcs = [
         "@bitstreams//:chip_earlgrey_cw340_bitstream",
-        "@bitstreams//:chip_earlgrey_cw340_otp_mmi",
-        "@bitstreams//:chip_earlgrey_cw340_rom_mmi",
+        "@bitstreams//:chip_earlgrey_cw340_mmi",
     ],
     design = "chip_earlgrey_cw340",
     manifest = "@bitstreams//:manifest",

hw/bitstream/cw340/BUILD

@@ -25,25 +25,13 @@ filegroup(
 )
 
 filegroup(
-    name = "rom_mmi",
+    name = "mmi",
     testonly = True,
     srcs = select({
         "//hw/bitstream:bitstream_skip": ["//hw/bitstream/universal:none"],
-        "//hw/bitstream:bitstream_vivado": ["//hw/bitstream/vivado:fpga_cw340_rom_mmi"],
-        "//hw/bitstream:bitstream_gcp_splice": ["@bitstreams//:chip_earlgrey_cw340_rom_mmi"],
-        "//conditions:default": ["@bitstreams//:chip_earlgrey_cw340_rom_mmi"],
-    }),
-    tags = ["manual"],
-)
-
-filegroup(
-    name = "otp_mmi",
-    testonly = True,
-    srcs = select({
-        "//hw/bitstream:bitstream_skip": ["//hw/bitstream/universal:none"],
-        "//hw/bitstream:bitstream_vivado": ["//hw/bitstream/vivado:fpga_cw340_otp_mmi"],
-        "//hw/bitstream:bitstream_gcp_splice": ["@bitstreams//:chip_earlgrey_cw340_otp_mmi"],
-        "//conditions:default": ["@bitstreams//:chip_earlgrey_cw340_otp_mmi"],
+        "//hw/bitstream:bitstream_vivado": ["//hw/bitstream/vivado:cw340_mmi"],
+        "//hw/bitstream:bitstream_gcp_splice": ["@bitstreams//:chip_earlgrey_cw340_mmi"],
+        "//conditions:default": ["@bitstreams//:chip_earlgrey_cw340_mmi"],
     }),
     tags = ["manual"],
 )
@@ -54,7 +42,8 @@ bitstream_splice(
     testonly = True,
     src = ":bitstream",
     data = "//sw/device/lib/testing/test_rom:test_rom_fpga_cw340_scr_vmem",
-    meminfo = ":rom_mmi",
+    instance = "rom",
+    meminfo = ":mmi",
     tags = ["manual"],
     update_usr_access = True,
 )
@@ -65,7 +54,8 @@ bitstream_splice(
     testonly = True,
     src = ":bitstream",
     data = "//sw/device/silicon_creator/rom:mask_rom_fpga_cw340_scr_vmem",
-    meminfo = ":rom_mmi",
+    instance = "rom",
+    meminfo = ":mmi",
     tags = ["manual"],
     update_usr_access = True,
 )
@@ -77,7 +67,8 @@ bitstream_splice(
         testonly = True,
         src = ":mask_rom",
         data = img_target,
-        meminfo = ":otp_mmi",
+        instance = "otp",
+        meminfo = ":mmi",
         tags = ["manual"],
         update_usr_access = True,
     )

hw/bitstream/hyperdebug/BUILD

@@ -21,25 +21,13 @@ filegroup(
 )
 
 filegroup(
-    name = "rom_mmi",
+    name = "mmi",
     testonly = True,
     srcs = select({
         "//hw/bitstream:bitstream_skip": ["//hw/bitstream/universal:none"],
-        "//hw/bitstream:bitstream_vivado": ["//hw/bitstream/vivado:rom_mmi_hyp"],
-        "//hw/bitstream:bitstream_gcp_splice": ["@bitstreams//:chip_earlgrey_cw310_hyperdebug_rom_mmi"],
-        "//conditions:default": ["@bitstreams//:chip_earlgrey_cw310_hyperdebug_rom_mmi"],
-    }),
-    tags = ["manual"],
-)
-
-filegroup(
-    name = "otp_mmi",
-    testonly = True,
-    srcs = select({
-        "//hw/bitstream:bitstream_skip": ["//hw/bitstream/universal:none"],
-        "//hw/bitstream:bitstream_vivado": ["//hw/bitstream/vivado:otp_mmi_hyp"],
-        "//hw/bitstream:bitstream_gcp_splice": ["@bitstreams//:chip_earlgrey_cw310_hyperdebug_otp_mmi"],
-        "//conditions:default": ["@bitstreams//:chip_earlgrey_cw310_hyperdebug_otp_mmi"],
+        "//hw/bitstream:bitstream_vivado": ["//hw/bitstream/vivado:cw310_hyperdebug_mmi"],
+        "//hw/bitstream:bitstream_gcp_splice": ["@bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi"],
+        "//conditions:default": ["@bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi"],
     }),
     tags = ["manual"],
 )
@@ -50,7 +38,8 @@ bitstream_splice(
     testonly = True,
     src = ":bitstream",
     data = "//sw/device/lib/testing/test_rom:test_rom_fpga_cw310_scr_vmem",
-    meminfo = ":rom_mmi",
+    instance = "rom",
+    meminfo = ":mmi",
     tags = ["manual"],
     update_usr_access = True,
 )
@@ -61,7 +50,8 @@ bitstream_splice(
     testonly = True,
     src = ":bitstream",
     data = "//sw/device/silicon_creator/rom:mask_rom_fpga_cw310_scr_vmem",
-    meminfo = ":rom_mmi",
+    instance = "rom",
+    meminfo = ":mmi",
     tags = ["manual"],
     update_usr_access = True,
 )
@@ -73,7 +63,8 @@ bitstream_splice(
         testonly = True,
         src = ":mask_rom",
         data = img_target,
-        meminfo = ":otp_mmi",
+        instance = "otp",
+        meminfo = ":mmi",
         tags = ["manual"],
         update_usr_access = True,
     )

hw/bitstream/universal/BUILD

@@ -29,8 +29,8 @@ label_flag(
 universal_splice(
     name = "splice",
     testonly = True,
-    # When the src bitstream, rom_mmi and otp_mmi fields are empty,
-    # the rule will use values from the exec_env.
+    # When the src bitstream and mmi fields are empty, the rule will use values
+    # from the exec_env.
     exec_env = ":env",
     otp = ":otp",
     rom = ":rom",