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Update google_riscv-dv to chipsalliance/riscv-dv@08b1206
Update code from upstream repository https://github.com/chipsalliance/riscv-dv to revision 08b12066b34c9728f706e45098ba502a36d7ca59 Signed-off-by: Marno van der Maas <[email protected]>
1 parent 44ed214 commit f60d03b

11 files changed

+294
-11
lines changed

‎vendor/google_riscv-dv.lock.hjson

+2-2
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88
{
99
upstream:
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{
11-
url: https://github.com/google/riscv-dv
12-
rev: 68ab8230c52ec66b393c04394aef4d6082ee53b4
11+
url: https://github.com/chipsalliance/riscv-dv
12+
rev: 08b12066b34c9728f706e45098ba502a36d7ca59
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}
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}

‎vendor/google_riscv-dv/pygen/pygen_src/test/.riscv_instr_base_test.py.swp

-12 KB
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‎vendor/google_riscv-dv/run.py

+7-1
Original file line numberDiff line numberDiff line change
@@ -139,6 +139,11 @@ def parse_iss_yaml(iss, iss_yaml, isa, setting_dir, debug_cmd):
139139
"""
140140
logging.info("Processing ISS setup file : {}".format(iss_yaml))
141141
yaml_data = read_yaml(iss_yaml)
142+
143+
# Path to the "scripts" subdirectory
144+
my_path = os.path.dirname(os.path.realpath(__file__))
145+
scripts_dir = os.path.join(my_path, "scripts") # Search for matched ISS
146+
142147
# Search for matched ISS
143148
for entry in yaml_data:
144149
if entry['iss'] == iss:
@@ -161,6 +166,7 @@ def parse_iss_yaml(iss, iss_yaml, isa, setting_dir, debug_cmd):
161166
cmd = re.sub("\<variant\>", variant, cmd)
162167
else:
163168
cmd = re.sub("\<variant\>", isa, cmd)
169+
cmd = re.sub("\<scripts_path\>", scripts_dir, cmd)
164170
return cmd
165171
logging.error("Cannot find ISS {}".format(iss))
166172
sys.exit(RET_FAIL)
@@ -662,7 +668,7 @@ def iss_sim(test_list, output_dir, iss_list, iss_yaml, iss_opts,
662668
prefix = ("{}/asm_test/{}_{}".format(
663669
output_dir, test['test'], i))
664670
elf = prefix + ".o"
665-
log = ("{}/{}.{}.log".format(log_dir, test['test'], i))
671+
log = ("{}/{}_{}.log".format(log_dir, test['test'], i))
666672
cmd = get_iss_cmd(base_cmd, elf, log)
667673
if 'iss_opts' in test:
668674
cmd += ' '

‎vendor/google_riscv-dv/scripts/renode_log_to_trace_csv.py

+156
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,156 @@
1+
#!/usr/bin/env python3
2+
"""
3+
Converts Renode log to execution trace for RISC-V DV
4+
"""
5+
6+
import argparse
7+
import os
8+
import re
9+
import sys
10+
import logging
11+
12+
sys.path.insert(0, os.path.dirname(os.path.realpath(__file__)))
13+
14+
from riscv_trace_csv import *
15+
from lib import *
16+
17+
# =============================================================================
18+
19+
GPR_NAMES = [
20+
("x0", "zero"),
21+
("x1", "ra"),
22+
("x2", "sp"),
23+
("x3", "gp"),
24+
("x4", "tp"),
25+
("x5", "t0"),
26+
("x6", "t1"),
27+
("x7", "t2"),
28+
("x8", "s0"),
29+
("x9", "s1"),
30+
("x10", "a0"),
31+
("x11", "a1"),
32+
("x12", "a2"),
33+
("x13", "a3"),
34+
("x14", "a4"),
35+
("x15", "a5"),
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("x16", "a6"),
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("x17", "a7"),
38+
("x18", "s2"),
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("x19", "s3"),
40+
("x20", "s4"),
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("x21", "s5"),
42+
("x22", "s6"),
43+
("x23", "s7"),
44+
("x24", "s8"),
45+
("x25", "s9"),
46+
("x26", "s10"),
47+
("x27", "s11"),
48+
("x28", "t3"),
49+
("x29", "t4"),
50+
("x30", "t5"),
51+
("x31", "t6"),
52+
]
53+
54+
# =============================================================================
55+
56+
57+
def process_renode_sim_log(log_name, csv_name):
58+
"""
59+
Converts a Renode trace log to CSV format
60+
"""
61+
62+
# Build lookups
63+
gpr_to_name = {m[0]: m[1] for m in GPR_NAMES}
64+
known_gpr = {m[0].upper() for m in GPR_NAMES}
65+
66+
# FIXME: We need a previous PC each time. Assume its value for the first
67+
# entry.
68+
prev_pc = "80000000"
69+
70+
# FIXME: Assume initial state of all GPR set to 0
71+
state = {m[0].upper(): "0" for m in GPR_NAMES}
72+
trace = []
73+
74+
with open(log_name, "r") as fp:
75+
for line in fp:
76+
77+
line = line.strip()
78+
if not line:
79+
continue
80+
81+
# Skip non-regdump
82+
if not line.startswith("REGDUMP:"):
83+
continue
84+
85+
# Decode state
86+
fields = line.replace("REGDUMP:", "").split(",")
87+
regs = {fields[i]: fields[i+1] for i in range(0, len(fields), 2)}
88+
89+
# Compute state difference
90+
diff = {r: regs[r] for r in known_gpr \
91+
if r in state and r in regs and state[r] != regs[r]}
92+
state = regs
93+
94+
# Format the entry
95+
entry = RiscvInstructionTraceEntry()
96+
entry.pc = prev_pc
97+
entry.binary = "0"
98+
entry.operand = ""
99+
entry.mode = "0"
100+
101+
# GPRs
102+
for x in range(32):
103+
name = "X{}".format(x)
104+
if name in diff:
105+
lname = name.lower()
106+
value = int(diff[name], 16)
107+
entry.gpr.append("{}:{:08x}".format(gpr_to_name[lname], value))
108+
109+
# CSRs
110+
# TODO:
111+
112+
# Add only if there is a GPR/CSR change
113+
if entry.gpr or entry.csr:
114+
trace.append(entry)
115+
116+
prev_pc = state["PC"]
117+
118+
return trace
119+
120+
121+
def write_csv(file_name, data):
122+
"""
123+
Writes the trace to CSV
124+
"""
125+
126+
with open(file_name, "w") as fp:
127+
128+
writer = RiscvInstructionTraceCsv(fp)
129+
writer.start_new_trace()
130+
131+
for entry in data:
132+
writer.write_trace_entry(entry)
133+
134+
# ============================================================================
135+
136+
137+
def main():
138+
# Parse input arguments
139+
parser = argparse.ArgumentParser()
140+
parser.add_argument("--log", type=str, help="Input Renode simulation log")
141+
parser.add_argument("--csv", type=str, help="Output trace CSV file")
142+
parser.add_argument("-v", "--verbose", dest="verbose", action="store_true",
143+
help="Verbose logging")
144+
parser.set_defaults(verbose=False)
145+
146+
args = parser.parse_args()
147+
setup_logging(args.verbose)
148+
149+
# Process Renode log
150+
trace = process_renode_sim_log(args.log, args.csv)
151+
# Write CSV
152+
write_csv(args.csv, trace)
153+
154+
155+
if __name__ == "__main__":
156+
main()

‎vendor/google_riscv-dv/scripts/renode_wrapper.py

+106
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,106 @@
1+
#!/usr/bin/env python3
2+
import argparse
3+
import subprocess
4+
import os
5+
import tempfile
6+
7+
# =============================================================================
8+
9+
REPL_TEMPLATE = """
10+
memory: Memory.MappedMemory @ sysbus 0x80000000
11+
size: 0x10000
12+
13+
cpu: CPU.RiscV32 @ sysbus
14+
cpuType: "{isa}"
15+
timeProvider: clint
16+
hartId: 0
17+
18+
clint: IRQControllers.CoreLevelInterruptor @ sysbus 0x02000000
19+
[0,1] -> cpu@[3,7]
20+
frequency: 1000000
21+
"""
22+
23+
RESC_TEMPLATE = """
24+
using sysbus
25+
mach create "riscv"
26+
machine LoadPlatformDescription @{repl}
27+
28+
sysbus LoadELF @{elf}
29+
30+
cpu MaximumBlockSize 1
31+
cpu SetHookAtBlockEnd "print('REGDUMP:' + ','.join(self.GetRegistersValues()))"
32+
33+
emulation RunFor "0.000100"
34+
35+
quit
36+
"""
37+
38+
# =============================================================================
39+
40+
41+
def main():
42+
"""
43+
The entry point
44+
"""
45+
46+
parser = argparse.ArgumentParser()
47+
48+
parser.add_argument(
49+
"--renode",
50+
type=str,
51+
default="renode",
52+
help="Path to Renode binary",
53+
)
54+
parser.add_argument(
55+
"--log",
56+
type=str,
57+
default=None,
58+
help="Output log file",
59+
)
60+
parser.add_argument(
61+
"--isa",
62+
type=str,
63+
default="rv32i",
64+
help="RISC-V ISA specification string",
65+
)
66+
parser.add_argument(
67+
"--elf",
68+
type=str,
69+
required=True,
70+
help="ELF file to run",
71+
)
72+
73+
args = parser.parse_args()
74+
75+
with tempfile.TemporaryDirectory() as tmpdir:
76+
77+
repl = os.path.join(tmpdir, "riscv.repl")
78+
resc = os.path.join(tmpdir, "riscv.resc")
79+
80+
params = {
81+
"renode": args.renode,
82+
"isa": args.isa,
83+
"elf": args.elf,
84+
"repl": repl,
85+
"resc": resc,
86+
"log": args.log,
87+
}
88+
89+
# Render REPL template
90+
with open(repl, "w") as fp:
91+
fp.write(REPL_TEMPLATE.format(**params))
92+
93+
# Render RESC template
94+
with open(resc, "w") as fp:
95+
fp.write(RESC_TEMPLATE.format(**params))
96+
97+
# Launch Renode, capture output
98+
cmd = "{renode} --console -p {resc}".format(**params)
99+
if args.log is not None:
100+
cmd += " &>{log}".format(**params)
101+
102+
subprocess.call(cmd, shell=True)
103+
104+
105+
if __name__ == "__main__":
106+
main()

‎vendor/google_riscv-dv/scripts/spike_log_to_trace_csv.py

+12-6
Original file line numberDiff line numberDiff line change
@@ -27,10 +27,12 @@
2727
from riscv_trace_csv import *
2828
from lib import *
2929

30-
RD_RE = re.compile(r"(core\s+\d+:\s+)?(?P<pri>\d) 0x(?P<addr>[a-f0-9]+?) " \
31-
"\((?P<bin>.*?)\) (?P<reg>[xf]\s*\d*?) 0x(?P<val>[a-f0-9]+)")
30+
RD_RE = re.compile(
31+
r"(core\s+\d+:\s+)?(?P<pri>\d)\s+0x(?P<addr>[a-f0-9]+?)\s+" \
32+
r"\((?P<bin>.*?)\)\s+(?P<reg>[xf]\s*\d*?)\s+0x(?P<val>[a-f0-9]+)" \
33+
r"(\s+(?P<csr>\S+)\s+0x(?P<csr_val>[a-f0-9]+))?")
3234
CORE_RE = re.compile(
33-
r"core\s+\d+:\s+0x(?P<addr>[a-f0-9]+?) \(0x(?P<bin>.*?)\) (?P<instr>.*?)$")
35+
r"core\s+\d+:\s+0x(?P<addr>[a-f0-9]+?)\s+\(0x(?P<bin>.*?)\)\s+(?P<instr>.*?)$")
3436
ADDR_RE = re.compile(
3537
r"(?P<rd>[a-z0-9]+?),(?P<imm>[\-0-9]+?)\((?P<rs1>[a-z0-9]+)\)")
3638
ILLE_RE = re.compile(r"trap_illegal_instruction")
@@ -173,9 +175,13 @@ def read_spike_trace(path, full_trace):
173175
# the --log-commits Spike option)?
174176
commit_match = RD_RE.match(line)
175177
if commit_match:
176-
instr.gpr.append(gpr_to_abi(commit_match.group('reg')
177-
.replace(' ', '')) +
178-
':' + commit_match.group('val'))
178+
groups = commit_match.groupdict()
179+
instr.gpr.append(gpr_to_abi(groups["reg"].replace(' ', '')) +
180+
":" + groups["val"])
181+
182+
if groups["csr"] and groups["csr_val"]:
183+
instr.csr.append(groups["csr"] + ":" + groups["csr_val"])
184+
179185
instr.mode = commit_match.group('pri')
180186

181187
# At EOF, we might have an instruction in hand. Yield it if so.

‎vendor/google_riscv-dv/scripts/whisper_log_trace_csv.py

+1
Original file line numberDiff line numberDiff line change
@@ -60,6 +60,7 @@ def process_whisper_sim_log(whisper_log, csv, full_trace=0):
6060
whisper_instr = m.group("instr").replace("\. + ", "")
6161
whisper_instr = whisper_instr.replace("\. - ", "-")
6262
rv_instr_trace = RiscvInstructionTraceEntry()
63+
rv_instr_trace.pc = m.group("pc")
6364
rv_instr_trace.instr_str = whisper_instr
6465
rv_instr_trace.binary = m.group("bin")
6566
reg = "x" + str(int(m.group("reg"), 16))

‎vendor/google_riscv-dv/src/isa/riscv_csr_instr.sv

+1-1
Original file line numberDiff line numberDiff line change
@@ -114,7 +114,7 @@ class riscv_csr_instr extends riscv_instr;
114114

115115
foreach (initial_csrs[r]) begin
116116
if (!(initial_csrs[r] inside {remove_csr})) begin
117-
include_write_reg.push_back(initial_csrs[r]);
117+
include_write_reg.push_back(privileged_reg_t'(initial_csrs[r]));
118118
end
119119
end
120120

‎vendor/google_riscv-dv/src/riscv_page_table_list.sv

+3
Original file line numberDiff line numberDiff line change
@@ -186,6 +186,9 @@ class riscv_page_table_list#(satp_mode_t MODE = SV39) extends uvm_object;
186186
$cast(valid_data_leaf_pte, valid_leaf_pte.clone());
187187
illegal_pte.turn_off_default_constraint();
188188
valid_link_pte.xwr = NEXT_LEVEL_PAGE;
189+
valid_link_pte.a = 1'b0;
190+
valid_link_pte.d = 1'b0;
191+
valid_link_pte.u = 1'b0;
189192
valid_link_pte.pack_entry();
190193
// Set data page to read/write, but not executable
191194
valid_data_leaf_pte.xwr = READ_WRITE_PAGE;

‎vendor/google_riscv-dv/yaml/iss.yaml

+5
Original file line numberDiff line numberDiff line change
@@ -36,3 +36,8 @@
3636
path_var: WHISPER_ISS
3737
cmd: >
3838
<path_var> <elf> --log --xlen <xlen> --isa <variant>
39+
40+
- iss: renode
41+
path_var: RENODE_PATH
42+
cmd: >
43+
python3 <scripts_path>/renode_wrapper.py --renode "<path_var>" --elf <elf> --isa <variant>

‎vendor/google_riscv-dv/yaml/simulator.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@
5353
- tool: questa
5454
compile:
5555
cmd:
56-
- "vmap mtiUvm $QUESTA_HOME/questasim/uvm-1.2"
56+
- "vmap mtiUvm $QUESTA_HOME/uvm-1.2"
5757
- "vlog -64
5858
+incdir+<setting>
5959
+incdir+<user_extension>

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