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andreaskurthandreaskurth
committedDec 19, 2024·
[rtl,pmp] Allow all accesses to Debug Module in debug mode
The RISC-V Debug Specification (current release 1.0.0-rc4) in Section A.2 states that the PMP must not disallow accesses to addresses of the Debug Module when the hart is in debug mode, regardless of how the PMP is configured. This commit changes the PMP accordingly. Signed-off-by: Andreas Kurth <[email protected]>
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‎doc/02_user/integration.rst

+6
Original file line numberDiff line numberDiff line change
@@ -108,6 +108,8 @@ Instantiation Template
108108
.RndCnstLfsrSeed ( ibex_pkg::RndCnstLfsrSeedDefault ),
109109
.RndCnstLfsrPerm ( ibex_pkg::RndCnstLfsrPermDefault ),
110110
.DbgTriggerEn ( 0 ),
111+
.DmBaseAddr ( 32'h1A110000 ),
112+
.DmAddrMask ( 32'h00000FFF ),
111113
.DmHaltAddr ( 32'h1A110800 ),
112114
.DmExceptionAddr ( 32'h1A110808 )
113115
) u_top (
@@ -224,6 +226,10 @@ Parameters
224226
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
225227
| ``DbgTriggerEn`` | bit | 0 | Enable debug trigger support (one trigger only) |
226228
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
229+
| ``DmBaseAddr`` | int | 0x1A110000 | Base address of the Debug Module |
230+
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
231+
| ``DmAddrMask`` | int | 0x1A110000 | Address mask of the Debug Module |
232+
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
227233
| ``DmHaltAddr`` | int | 0x1A110800 | Address to jump to when entering Debug Mode |
228234
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
229235
| ``DmExceptionAddr`` | int | 0x1A110808 | Address to jump to when an exception occurs while in Debug Mode |

‎doc/03_reference/debug.rst

+4
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,10 @@ Parameters
3232
+---------------------+-----------------------------------------------------------------+
3333
| Parameter | Description |
3434
+=====================+=================================================================+
35+
| ``DmBaseAddr`` | Base address of the Debug Module |
36+
+---------------------+-----------------------------------------------------------------+
37+
| ``DmAddrMask`` | Address mask of the Debug Module |
38+
+---------------------+-----------------------------------------------------------------+
3539
| ``DmHaltAddr`` | Address to jump to when entering Debug Mode |
3640
+---------------------+-----------------------------------------------------------------+
3741
| ``DmExceptionAddr`` | Address to jump to when an exception occurs while in Debug Mode |

‎doc/03_reference/pmp.rst

+6
Original file line numberDiff line numberDiff line change
@@ -52,3 +52,9 @@ By default all PMP CSRs (include ``mseccfg``) are reset to 0.
5252
Some applications may want other reset values.
5353
Default reset values are defined in :file:`ibex_pkg.sv`.
5454
An implementation can either modify this file or pass custom reset values as a module parameter.
55+
56+
Debug Mode
57+
----------
58+
59+
In debug mode, the PMP allows all accesses to addresses of the Debug Module, as defined by the `DmBaseAddr` and `DmAddrMask` module parameters.
60+
This is mandated by the RISC-V Debug Specification (v1.0.0).

‎dv/riscv_compliance/rtl/ibex_riscv_compliance.sv

+2
Original file line numberDiff line numberDiff line change
@@ -155,6 +155,8 @@ module ibex_riscv_compliance (
155155
.DbgTriggerEn (DbgTriggerEn ),
156156
.SecureIbex (SecureIbex ),
157157
.ICacheScramble (ICacheScramble ),
158+
.DmBaseAddr (32'h00000000 ),
159+
.DmAddrMask (32'h00000003 ),
158160
.DmHaltAddr (32'h00000000 ),
159161
.DmExceptionAddr (32'h00000000 )
160162
) u_top (

‎dv/uvm/core_ibex/tb/core_ibex_tb_top.sv

+2
Original file line numberDiff line numberDiff line change
@@ -84,6 +84,8 @@ module core_ibex_tb_top;
8484
assign {scramble_key, scramble_nonce} = scrambling_key_if.d_data;
8585

8686
ibex_top_tracing #(
87+
.DmBaseAddr (32'h`BOOT_ADDR ),
88+
.DmAddrMask (32'h0000_0007 ),
8789
.DmHaltAddr (32'h`BOOT_ADDR + 'h0 ),
8890
.DmExceptionAddr (32'h`BOOT_ADDR + 'h4 ),
8991
.PMPEnable (PMPEnable ),

‎examples/simple_system/rtl/ibex_simple_system.sv

+2
Original file line numberDiff line numberDiff line change
@@ -204,6 +204,8 @@ module ibex_simple_system (
204204
.WritebackStage ( WritebackStage ),
205205
.BranchPredictor ( BranchPredictor ),
206206
.DbgTriggerEn ( DbgTriggerEn ),
207+
.DmBaseAddr ( 32'h00100000 ),
208+
.DmAddrMask ( 32'h00000003 ),
207209
.DmHaltAddr ( 32'h00100000 ),
208210
.DmExceptionAddr ( 32'h00100000 )
209211
) u_top (

‎rtl/ibex_core.sv

+5
Original file line numberDiff line numberDiff line change
@@ -44,6 +44,8 @@ module ibex_core import ibex_pkg::*; #(
4444
parameter int unsigned RegFileDataWidth = 32,
4545
parameter bit MemECC = 1'b0,
4646
parameter int unsigned MemDataWidth = MemECC ? 32 + 7 : 32,
47+
parameter int unsigned DmBaseAddr = 32'h1A110000,
48+
parameter int unsigned DmAddrMask = 32'h00000FFF,
4749
parameter int unsigned DmHaltAddr = 32'h1A110800,
4850
parameter int unsigned DmExceptionAddr = 32'h1A110808
4951
) (
@@ -1177,6 +1179,8 @@ module ibex_core import ibex_pkg::*; #(
11771179
assign pmp_priv_lvl[PMP_D] = priv_mode_lsu;
11781180

11791181
ibex_pmp #(
1182+
.DmBaseAddr (DmBaseAddr),
1183+
.DmAddrMask (DmAddrMask),
11801184
.PMPGranularity(PMPGranularity),
11811185
.PMPNumChan (PMPNumChan),
11821186
.PMPNumRegions (PMPNumRegions)
@@ -1185,6 +1189,7 @@ module ibex_core import ibex_pkg::*; #(
11851189
.csr_pmp_cfg_i (csr_pmp_cfg),
11861190
.csr_pmp_addr_i (csr_pmp_addr),
11871191
.csr_pmp_mseccfg_i(csr_pmp_mseccfg),
1192+
.debug_mode_i (debug_mode),
11881193
.priv_mode_i (pmp_priv_lvl),
11891194
// Access checking channels
11901195
.pmp_req_addr_i (pmp_req_addr),

‎rtl/ibex_lockstep.sv

+4
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,8 @@ module ibex_lockstep import ibex_pkg::*; #(
4040
parameter int unsigned RegFileDataWidth = 32,
4141
parameter bit MemECC = 1'b0,
4242
parameter int unsigned MemDataWidth = MemECC ? 32 + 7 : 32,
43+
parameter int unsigned DmBaseAddr = 32'h1A110000,
44+
parameter int unsigned DmAddrMask = 32'h00000FFF,
4345
parameter int unsigned DmHaltAddr = 32'h1A110800,
4446
parameter int unsigned DmExceptionAddr = 32'h1A110808
4547
) (
@@ -377,6 +379,8 @@ module ibex_lockstep import ibex_pkg::*; #(
377379
.RegFileDataWidth ( RegFileDataWidth ),
378380
.MemECC ( MemECC ),
379381
.MemDataWidth ( MemDataWidth ),
382+
.DmBaseAddr ( DmBaseAddr ),
383+
.DmAddrMask ( DmAddrMask ),
380384
.DmHaltAddr ( DmHaltAddr ),
381385
.DmExceptionAddr ( DmExceptionAddr )
382386
) u_shadow_core (

‎rtl/ibex_pmp.sv

+16-1
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,8 @@
55
`include "dv_fcov_macros.svh"
66

77
module ibex_pmp #(
8+
parameter int unsigned DmBaseAddr = 32'h1A110000,
9+
parameter int unsigned DmAddrMask = 32'h00000FFF,
810
// Granularity of NAPOT access,
911
// 0 = No restriction, 1 = 8 byte, 2 = 16 byte, 3 = 32 byte, etc.
1012
parameter int unsigned PMPGranularity = 0,
@@ -18,6 +20,8 @@ module ibex_pmp #(
1820
input logic [33:0] csr_pmp_addr_i [PMPNumRegions],
1921
input ibex_pkg::pmp_mseccfg_t csr_pmp_mseccfg_i,
2022

23+
input logic debug_mode_i,
24+
2125
input ibex_pkg::priv_lvl_e priv_mode_i [PMPNumChan],
2226
// Access checking channels
2327
input logic [33:0] pmp_req_addr_i [PMPNumChan],
@@ -37,6 +41,7 @@ module ibex_pmp #(
3741
logic [PMPNumChan-1:0][PMPNumRegions-1:0] region_match_all;
3842
logic [PMPNumChan-1:0][PMPNumRegions-1:0] region_basic_perm_check;
3943
logic [PMPNumChan-1:0][PMPNumRegions-1:0] region_perm_check;
44+
logic [PMPNumChan-1:0] debug_mode_allowed_access;
4045

4146
///////////////////////
4247
// Functions for PMP //
@@ -48,6 +53,7 @@ module ibex_pmp #(
4853
// |
4954
// region_match_all --------------------------------> access_fault_check <----------
5055
// |
56+
// !debug_mode_allowed_access ------------------------------> &
5157
// \--> pmp_req_err_o
5258

5359
// Compute permissions checks that apply when MSECCFG.MML is set. Added for Smepmp support.
@@ -226,9 +232,18 @@ module ibex_pmp #(
226232
pmp_req_addr_i[c][PMPGranularity+2-1:0]};
227233
end
228234

235+
// Determine whether the core is in debug mode and the access is to an address in the range of
236+
// the Debug Module. According to Section A.2 of the RISC-V Debug Specification, the PMP must
237+
// not disallow fetches, loads, or stores in the address range associated with the Debug Module
238+
// when the hart is in debug mode.
239+
assign debug_mode_allowed_access[c] = debug_mode_i &
240+
((pmp_req_addr_i[c][31:0] & ~DmAddrMask) == DmBaseAddr);
241+
229242
// Once the permission checks of the regions are done, decide if the access is
230243
// denied by figuring out the matching region and its permission check.
231-
assign pmp_req_err_o[c] = access_fault_check(csr_pmp_mseccfg_i.mmwp,
244+
// No error is raised if the access is allowed as Debug Module access (first term).
245+
assign pmp_req_err_o[c] = ~debug_mode_allowed_access[c] &
246+
access_fault_check(csr_pmp_mseccfg_i.mmwp,
232247
csr_pmp_mseccfg_i.mml,
233248
pmp_req_type_i[c],
234249
region_match_all[c],

‎rtl/ibex_top.sv

+10
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,8 @@ module ibex_top import ibex_pkg::*; #(
3737
parameter int unsigned ICacheScrNumPrinceRoundsHalf = 2,
3838
parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault,
3939
parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault,
40+
parameter int unsigned DmBaseAddr = 32'h1A110000,
41+
parameter int unsigned DmAddrMask = 32'h00000FFF,
4042
parameter int unsigned DmHaltAddr = 32'h1A110800,
4143
parameter int unsigned DmExceptionAddr = 32'h1A110808,
4244
// Default seed and nonce for scrambling
@@ -313,6 +315,8 @@ module ibex_top import ibex_pkg::*; #(
313315
.RegFileDataWidth (RegFileDataWidth),
314316
.MemECC (MemECC),
315317
.MemDataWidth (MemDataWidth),
318+
.DmBaseAddr (DmBaseAddr),
319+
.DmAddrMask (DmAddrMask),
316320
.DmHaltAddr (DmHaltAddr),
317321
.DmExceptionAddr (DmExceptionAddr)
318322
) u_ibex_core (
@@ -1016,6 +1020,8 @@ module ibex_top import ibex_pkg::*; #(
10161020
.RegFileECC (RegFileECC),
10171021
.RegFileDataWidth (RegFileDataWidth),
10181022
.MemECC (MemECC),
1023+
.DmBaseAddr (DmBaseAddr),
1024+
.DmAddrMask (DmAddrMask),
10191025
.DmHaltAddr (DmHaltAddr),
10201026
.DmExceptionAddr (DmExceptionAddr)
10211027
) u_ibex_lockstep (
@@ -1120,6 +1126,10 @@ module ibex_top import ibex_pkg::*; #(
11201126
assign alert_major_bus_o = core_alert_major_bus | lockstep_alert_major_bus;
11211127
assign alert_minor_o = core_alert_minor | lockstep_alert_minor;
11221128

1129+
// Parameter assertions
1130+
`ASSERT_INIT(DmHaltAddrInRange_A, (DmHaltAddr & ~DmAddrMask) == DmBaseAddr)
1131+
`ASSERT_INIT(DmExceptionAddrInRange_A, (DmExceptionAddr & ~DmAddrMask) == DmBaseAddr)
1132+
11231133
// X checks for top-level outputs
11241134
`ASSERT_KNOWN(IbexInstrReqX, instr_req_o)
11251135
`ASSERT_KNOWN_IF(IbexInstrReqPayloadX, instr_addr_o, instr_req_o)

‎rtl/ibex_top_tracing.sv

+4
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,8 @@ module ibex_top_tracing import ibex_pkg::*; #(
2727
parameter bit ICacheScramble = 1'b0,
2828
parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault,
2929
parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault,
30+
parameter int unsigned DmBaseAddr = 32'h1A110000,
31+
parameter int unsigned DmAddrMask = 32'h00000FFF,
3032
parameter int unsigned DmHaltAddr = 32'h1A110800,
3133
parameter int unsigned DmExceptionAddr = 32'h1A110808
3234
) (
@@ -184,6 +186,8 @@ module ibex_top_tracing import ibex_pkg::*; #(
184186
.ICacheScramble ( ICacheScramble ),
185187
.RndCnstLfsrSeed ( RndCnstLfsrSeed ),
186188
.RndCnstLfsrPerm ( RndCnstLfsrPerm ),
189+
.DmBaseAddr ( DmBaseAddr ),
190+
.DmAddrMask ( DmAddrMask ),
187191
.DmHaltAddr ( DmHaltAddr ),
188192
.DmExceptionAddr ( DmExceptionAddr )
189193
) u_ibex_top (

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