diff --git a/llvm/utils/TableGen/Common/CodeGenSchedule.cpp b/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
index ce03bfc73e770..7ae18d3ccc7bc 100644
--- a/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
@@ -979,8 +979,9 @@ unsigned CodeGenSchedModels::addSchedClass(const Record *ItinClassDef,
     return SC.isKeyEqual(ItinClassDef, OperWrites, OperReads);
   };
 
-  auto I = find_if(make_range(schedClassBegin(), schedClassEnd()), IsKeyEqual);
-  unsigned Idx = I == schedClassEnd() ? 0 : std::distance(schedClassBegin(), I);
+  auto I = find_if(SchedClasses, IsKeyEqual);
+  unsigned Idx =
+      I == SchedClasses.end() ? 0 : std::distance(SchedClasses.begin(), I);
   if (Idx || SchedClasses[0].isKeyEqual(ItinClassDef, OperWrites, OperReads)) {
     IdxVec PI;
     std::set_union(SchedClasses[Idx].ProcIndices.begin(),
@@ -1103,8 +1104,7 @@ void CodeGenSchedModels::createInstRWClass(const Record *InstRWDef) {
 
 // True if collectProcItins found anything.
 bool CodeGenSchedModels::hasItineraries() const {
-  for (const CodeGenProcModel &PM :
-       make_range(procModelBegin(), procModelEnd()))
+  for (const CodeGenProcModel &PM : procModels())
     if (PM.hasItineraries())
       return true;
   return false;
@@ -1129,8 +1129,7 @@ void CodeGenSchedModels::collectProcItins() {
       const Record *ItinDef = ItinData->getValueAsDef("TheClass");
       bool FoundClass = false;
 
-      for (const CodeGenSchedClass &SC :
-           make_range(schedClassBegin(), schedClassEnd())) {
+      for (const CodeGenSchedClass &SC : schedClasses()) {
         // Multiple SchedClasses may share an itinerary. Update all of them.
         if (SC.ItinClassDef == ItinDef) {
           ProcModel.ItinDefList[SC.Index] = ItinData;
@@ -1420,8 +1419,7 @@ void PredTransitions::getIntersectingVariants(
     if (AliasProcIdx && AliasProcIdx != TransVec[TransIdx].ProcIndex)
       continue;
     if (!Variants.empty()) {
-      const CodeGenProcModel &PM =
-          *(SchedModels.procModelBegin() + AliasProcIdx);
+      const CodeGenProcModel &PM = SchedModels.procModels()[AliasProcIdx];
       PrintFatalError((*AI)->getLoc(),
                       "Multiple variants defined for processor " +
                           PM.ModelName +
@@ -1834,8 +1832,7 @@ void CodeGenSchedModels::collectProcResources() {
   // Add any subtarget-specific SchedReadWrites that are directly associated
   // with processor resources. Refer to the parent SchedClass's ProcIndices to
   // determine which processors they apply to.
-  for (const CodeGenSchedClass &SC :
-       make_range(schedClassBegin(), schedClassEnd())) {
+  for (const CodeGenSchedClass &SC : schedClasses()) {
     if (SC.ItinClassDef) {
       collectItinProcResources(SC.ItinClassDef);
       continue;
diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp
index 9bd18f5837eea..1120f06875c77 100644
--- a/llvm/utils/TableGen/SubtargetEmitter.cpp
+++ b/llvm/utils/TableGen/SubtargetEmitter.cpp
@@ -1104,8 +1104,7 @@ void SubtargetEmitter::genSchedClassTables(const CodeGenProcModel &ProcModel,
 
     // A Variant SchedClass has no resources of its own.
     bool HasVariants = false;
-    for (const CodeGenSchedTransition &CGT :
-         make_range(SC.Transitions.begin(), SC.Transitions.end())) {
+    for (const CodeGenSchedTransition &CGT : SC.Transitions) {
       if (CGT.ProcIndex == ProcModel.Index) {
         HasVariants = true;
         break;