ModulePrefixAnnotation not working properly on aggregate-typed cmems

[jackkoenig]

Consider the following FIRRTL

FIRRTL version 4.0.0
circuit Top : %[[
  {
    "class":"chisel3.ModulePrefixAnnotation",
    "target": "~Top|Top>ram",
    "prefix":"Foo_"
  },
  {
    "class":"chisel3.ModulePrefixAnnotation",
    "target": "~Top|Top>ram2",
    "prefix":"Foo_"
  }
]]
  public module Top :
    input clock : Clock
    input raddr : UInt<6>
    input waddr : UInt<6>
    input wdata : { foo : UInt<8>, bar : UInt<8> }
    output rdata : UInt<24>

    cmem ram : { foo : UInt<8>, bar : UInt<8> }[64]

    write mport w = ram[waddr], clock
    connect w, wdata

    read mport r = ram[raddr], clock

    cmem ram2 : UInt<8>[64]

    write mport w2 = ram2[waddr], clock
    connect w2, wdata.foo

    read mport r2 = ram2[raddr], clock

    connect rdata, cat(r2, cat(r.foo, r.bar))

Here we have ram which has a Bundle data type and ram2 which has UInt<8> as its data type.

If you compile this with firtool 1.92.0 you'll get the following Verilog instances:

  ram_64x16 ram_ext (
    ...
  Foo_ram2_64x8 ram2_ext (

ram2 gets prefixed properly, but ram does not.

[youngar]

With the linked change the output is:

  Foo_ram_64x16 ram_ext (
    .R0_addr (raddr),
    .R0_en   (1'h1),
    .R0_clk  (clock),
    .R0_data (_ram_ext_R0_data),
    .W0_addr (waddr),
    .W0_en   (1'h1),
    .W0_clk  (clock),
    .W0_data ({wdata_foo, wdata_bar})
  );
  Foo_ram2_64x8 ram2_ext (
    .R0_addr (raddr),
    .R0_en   (1'h1),
    .R0_clk  (clock),
    .R0_data (_ram2_ext_R0_data),
    .W0_addr (waddr),
    .W0_en   (1'h1),
    .W0_clk  (clock),
    .W0_data (wdata_foo)
  );