diff --git a/DemoWithMemCfg.vhf b/DemoWithMemCfg.vhf
index e0978f4..cd3b7ff 100644
--- a/DemoWithMemCfg.vhf
+++ b/DemoWithMemCfg.vhf
@@ -7,11 +7,11 @@
 -- \   \   \/     Version : 14.7
 --  \   \         Application : sch2hdl
 --  /   /         Filename : DemoWithMemCfg.vhf
--- /___/   /\     Timestamp : 12/07/2020 12:52:34
+-- /___/   /\     Timestamp : 12/05/2020 01:19:40
 -- \   \  /  \ 
 --  \___\/\___\ 
 --
---Command: sch2hdl -intstyle ise -family spartan3e -flat -suppress -vhdl /home/user/workspace/nexys2bist1200original/DemoWithMemCfg.vhf -w /home/user/workspace/nexys2bist1200original/DemoWithMemCfg.sch
+--Command: /home/user/.local/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/sch2hdl -intstyle ise -family spartan3e -flat -suppress -vhdl /home/user/workspace/nexys2bist1200/DemoWithMemCfg.vhf -w /home/user/workspace/nexys2bist1200/DemoWithMemCfg.sch
 --Design Name: DemoWithMemCfg
 --Device: spartan3e
 --Purpose:
@@ -39,29 +39,29 @@ end VgaPs2Demo_MUSER_DemoWithMemCfg;
 
 architecture BEHAVIORAL of VgaPs2Demo_MUSER_DemoWithMemCfg is
    attribute BOX_TYPE   : string ;
-   signal ck25MHz    : std_logic;
-   signal ck100MHz   : std_logic;
-   signal XLXN_50    : std_logic_vector (9 downto 0);
-   signal XLXN_60    : std_logic;
-   signal XLXN_61    : std_logic;
-   signal XLXN_62    : std_logic;
-   signal XLXN_64    : std_logic_vector (7 downto 0);
-   signal XLXN_77    : std_logic_vector (9 downto 0);
-   signal XLXN_131   : std_logic_vector (9 downto 0);
-   signal XLXN_132   : std_logic_vector (7 downto 0);
-   signal XLXN_156   : std_logic;
-   signal XLXN_157   : std_logic;
-   signal XLXN_159   : std_logic;
-   signal XLXN_457   : std_logic;
-   signal XLXN_469   : std_logic_vector (13 downto 0);
-   signal XLXN_470   : std_logic_vector (3 downto 0);
-   signal XLXN_471   : std_logic_vector (3 downto 0);
-   signal XLXN_472   : std_logic_vector (3 downto 0);
-   signal XLXN_473   : std_logic_vector (3 downto 0);
-   signal XLXN_474   : std_logic_vector (3 downto 0);
-   signal XLXN_475   : std_logic_vector (3 downto 0);
-   signal XLXN_490   : std_logic_vector (10 downto 0);
-   signal XLXN_491   : std_logic_vector (10 downto 0);
+   signal ck25MHz    : std_logic := '0';
+   signal ck100MHz   : std_logic := '0';
+   signal XLXN_50    : std_logic_vector (9 downto 0) := (others => '0');
+   signal XLXN_60    : std_logic := '0';
+   signal XLXN_61    : std_logic := '0';
+   signal XLXN_62    : std_logic := '0';
+   signal XLXN_64    : std_logic_vector (7 downto 0) := (others => '0');
+   signal XLXN_77    : std_logic_vector (9 downto 0) := (others => '0');
+   signal XLXN_131   : std_logic_vector (9 downto 0) := (others => '0');
+   signal XLXN_132   : std_logic_vector (7 downto 0) := (others => '0');
+   signal XLXN_156   : std_logic := '0';
+   signal XLXN_157   : std_logic := '0';
+   signal XLXN_159   : std_logic := '0';
+   signal XLXN_457   : std_logic := '0';
+   signal XLXN_469   : std_logic_vector (13 downto 0) := (others => '0');
+   signal XLXN_470   : std_logic_vector (3 downto 0) := (others => '0');
+   signal XLXN_471   : std_logic_vector (3 downto 0) := (others => '0');
+   signal XLXN_472   : std_logic_vector (3 downto 0) := (others => '0');
+   signal XLXN_473   : std_logic_vector (3 downto 0) := (others => '0');
+   signal XLXN_474   : std_logic_vector (3 downto 0) := (others => '0');
+   signal XLXN_475   : std_logic_vector (3 downto 0) := (others => '0');
+   signal XLXN_490   : std_logic_vector (10 downto 0) := (others => '0');
+   signal XLXN_491   : std_logic_vector (10 downto 0) := (others => '0');
    component clkdllctrl
       port ( ckDivOut : inout   std_logic; 
              ckOut    : inout std_logic; 
@@ -259,6 +259,9 @@ end BEHAVIORAL;
 
 
 
+
+
+
 library ieee;
 use ieee.std_logic_1164.ALL;
 use ieee.numeric_std.ALL;
@@ -313,54 +316,54 @@ end DemoWithMemCfg;
 
 architecture BEHAVIORAL of DemoWithMemCfg is
    attribute BOX_TYPE   : string ;
-   signal XLXN_1487     : std_logic_vector (7 downto 0);
-   signal XLXN_1488     : std_logic;
-   signal XLXN_1526     : std_logic_vector (7 downto 0);
-   signal XLXN_1527     : std_logic;
-   signal XLXN_1579     : std_logic;
-   signal XLXN_1747     : std_logic_vector (3 downto 0);
-   signal XLXN_1748     : std_logic_vector (3 downto 0);
-   signal XLXN_1749     : std_logic_vector (3 downto 0);
-   signal XLXN_1750     : std_logic;
-   signal XLXN_1751     : std_logic;
-   signal XLXN_1848     : std_logic_vector (3 downto 0);
-   signal XLXN_1849     : std_logic;
-   signal XLXN_1852     : std_logic_vector (6 downto 0);
-   signal XLXN_1882     : std_logic;
-   signal XLXN_1902     : std_logic;
-   signal XLXN_1938     : std_logic;
-   signal XLXN_1939     : std_logic_vector (6 downto 0);
-   signal XLXN_1940     : std_logic_vector (3 downto 0);
-   signal XLXN_1944     : std_logic_vector (7 downto 0);
-   signal XLXN_1947     : std_logic;
-   signal XLXN_1948     : std_logic;
-   signal XLXN_1949     : std_logic;
-   signal XLXN_2184     : std_logic_vector (7 downto 0);
-   signal XLXN_2186     : std_logic_vector (7 downto 0);
-   signal XLXN_2187     : std_logic_vector (7 downto 0);
-   signal XLXN_2196     : std_logic_vector (7 downto 0);
-   signal XLXN_2212     : std_logic_vector (47 downto 0);
-   signal XLXN_2230     : std_logic_vector (7 downto 0);
-   signal XLXN_2235     : std_logic;
-   signal XLXN_2236     : std_logic;
-   signal XLXN_2237     : std_logic;
-   signal XLXN_2238     : std_logic;
-   signal XLXN_2239     : std_logic;
-   signal XLXN_2252     : std_logic;
-   signal XLXN_2549     : std_logic_vector (7 downto 0);
-   signal XLXN_2550     : std_logic_vector (1 downto 0);
-   signal XLXN_2570     : std_logic;
-   signal RamLB_DUMMY   : std_logic;
-   signal MemOe_DUMMY   : std_logic;
-   signal RamAdv_DUMMY  : std_logic;
-   signal FlashRp_DUMMY : std_logic;
-   signal RamUB_DUMMY   : std_logic;
-   signal RamCS_DUMMY   : std_logic;
-   signal MemWr_DUMMY   : std_logic;
-   signal FlashCS_DUMMY : std_logic;
-   signal MemAdr_DUMMY  : std_logic_vector (23 downto 1);
-   signal RamCre_DUMMY  : std_logic;
-   signal RamClk_DUMMY  : std_logic;
+   signal XLXN_1487     : std_logic_vector (7 downto 0) := (others => '0');
+   signal XLXN_1488     : std_logic := '0';
+   signal XLXN_1526     : std_logic_vector (7 downto 0) := (others => '0');
+   signal XLXN_1527     : std_logic := '0';
+   signal XLXN_1579     : std_logic := '0';
+   signal XLXN_1747     : std_logic_vector (3 downto 0) := (others => '0');
+   signal XLXN_1748     : std_logic_vector (3 downto 0) := (others => '0');
+   signal XLXN_1749     : std_logic_vector (3 downto 0) := (others => '0');
+   signal XLXN_1750     : std_logic := '0';
+   signal XLXN_1751     : std_logic := '0';
+   signal XLXN_1848     : std_logic_vector (3 downto 0) := (others => '0');
+   signal XLXN_1849     : std_logic := '0';
+   signal XLXN_1852     : std_logic_vector (6 downto 0) := (others => '0');
+   signal XLXN_1882     : std_logic := '0';
+   signal XLXN_1902     : std_logic := '0';
+   signal XLXN_1938     : std_logic := '0';
+   signal XLXN_1939     : std_logic_vector (6 downto 0) := (others => '0');
+   signal XLXN_1940     : std_logic_vector (3 downto 0) := (others => '0');
+   signal XLXN_1944     : std_logic_vector (7 downto 0) := (others => '0');
+   signal XLXN_1947     : std_logic := '0';
+   signal XLXN_1948     : std_logic := '0';
+   signal XLXN_1949     : std_logic := '0';
+   signal XLXN_2184     : std_logic_vector (7 downto 0) := (others => '0');
+   signal XLXN_2186     : std_logic_vector (7 downto 0) := (others => '0');
+   signal XLXN_2187     : std_logic_vector (7 downto 0) := (others => '0');
+   signal XLXN_2196     : std_logic_vector (7 downto 0) := (others => '0');
+   signal XLXN_2212     : std_logic_vector (47 downto 0) := (others => '0');
+   signal XLXN_2230     : std_logic_vector (7 downto 0) := (others => '0');
+   signal XLXN_2235     : std_logic := '0';
+   signal XLXN_2236     : std_logic := '0';
+   signal XLXN_2237     : std_logic := '0';
+   signal XLXN_2238     : std_logic := '0';
+   signal XLXN_2239     : std_logic := '0';
+   signal XLXN_2252     : std_logic := '0';
+   signal XLXN_2549     : std_logic_vector (7 downto 0) := (others => '0');
+   signal XLXN_2550     : std_logic_vector (1 downto 0) := (others => '0');
+   signal XLXN_2570     : std_logic := '0';
+   signal RamLB_DUMMY   : std_logic := '0';
+   signal MemOe_DUMMY   : std_logic := '0';
+   signal RamAdv_DUMMY  : std_logic := '0';
+   signal FlashRp_DUMMY : std_logic := '0';
+   signal RamUB_DUMMY   : std_logic := '0';
+   signal RamCS_DUMMY   : std_logic := '0';
+   signal MemWr_DUMMY   : std_logic := '0';
+   signal FlashCS_DUMMY : std_logic := '0';
+   signal MemAdr_DUMMY  : std_logic_vector (23 downto 1) := (others => '0');
+   signal RamCre_DUMMY  : std_logic := '0';
+   signal RamClk_DUMMY  : std_logic := '0';
    component BlockRamCtrl
       port ( UsbClk       : in    std_logic; 
              UsbDBOut     : out   std_logic_vector (7 downto 0); 
@@ -674,7 +677,7 @@ begin
                 HandShakeReqIn=>XLXN_1948,
                 busEppOut(7 downto 0)=>XLXN_2184(7 downto 0),
                 ctlEppDwrOut=>XLXN_2252,
-                ctlEppStartOut=>XLXN_1579,
+                ctlEppStartOut=>XLXN_1579, -- xxx XLXN_1579 memctrl ctlMsmStartIn (ctlEppStartOut <= '1' when stEppCur = stEppLaunchProc else '0';)
                 EppDBOut(7 downto 0)=>XLXN_1526(7 downto 0),
                 EppWait=>XLXN_1527,
                 ctlEppRdCycleOut=>XLXN_1947,
@@ -685,7 +688,7 @@ begin
                 ComponentSelect=>XLXN_2239,
                 ctlEppRdCycleIn=>XLXN_1947,
                 ctlMsmDwrIn=>XLXN_2252,
-                ctlMsmStartIn=>XLXN_1938,
+                ctlMsmStartIn=>XLXN_1938, -- xxx gnd
                 EppWrDataIn(7 downto 0)=>XLXN_2184(7 downto 0),
                 FlashStSts=>FlashStSts,
                 RamWait=>RamWait,
@@ -780,7 +783,7 @@ begin
                 ComponentSelect=>XLXN_2238,
                 ctlEppRdCycleIn=>XLXN_1947,
                 ctlMsmDwrIn=>XLXN_2252,
-                ctlMsmStartIn=>XLXN_1579,
+                ctlMsmStartIn=>XLXN_1579, -- xxx eppctrl
                 EppWrDataIn(7 downto 0)=>XLXN_2184(7 downto 0),
                 FlashStSts=>FlashStSts,
                 RamWait=>RamWait,
@@ -790,7 +793,7 @@ begin
                 FlashByte=>open,
                 FlashCS=>FlashCS_DUMMY,
                 FlashRp=>FlashRp_DUMMY,
-                HandShakeReqOut=>XLXN_1948,
+                HandShakeReqOut=>XLXN_1948, -- xxx eppctrl
                 MemAdr(23 downto 1)=>MemAdr_DUMMY(23 downto 1),
                 MemCtrlEnabled=>open,
                 MemOE=>MemOe_DUMMY,
diff --git a/DemoWithMemTestMemCfgSyncVgaPs2.xise b/DemoWithMemTestMemCfgSyncVgaPs2.xise
index a00d76d..3e8ec6b 100644
--- a/DemoWithMemTestMemCfgSyncVgaPs2.xise
+++ b/DemoWithMemTestMemCfgSyncVgaPs2.xise
@@ -19,18 +19,18 @@
     <file xil_pn:name="Synchro.sym" xil_pn:type="FILE_SYMBOL"/>
     <file xil_pn:name="DispCtrl.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
     </file>
     <file xil_pn:name="Demo.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
     </file>
     <file xil_pn:name="sinv.sym" xil_pn:type="FILE_SYMBOL"/>
     <file xil_pn:name="EppCtrl.sym" xil_pn:type="FILE_SYMBOL"/>
     <file xil_pn:name="VideoRom.sym" xil_pn:type="FILE_SYMBOL"/>
     <file xil_pn:name="EppCtrl.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
     </file>
     <file xil_pn:name="ps2interface.sym" xil_pn:type="FILE_SYMBOL"/>
     <file xil_pn:name="DemoWithMemCfg.sym" xil_pn:type="FILE_SYMBOL"/>
@@ -40,26 +40,26 @@
     <file xil_pn:name="Demo.sym" xil_pn:type="FILE_SYMBOL"/>
     <file xil_pn:name="VideoRom.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
     </file>
     <file xil_pn:name="PinDrivers.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
     </file>
     <file xil_pn:name="MouseCursor.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
     </file>
     <file xil_pn:name="dispMux.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
     </file>
     <file xil_pn:name="PinDrivers.sym" xil_pn:type="FILE_SYMBOL"/>
     <file xil_pn:name="Vga12to8.sym" xil_pn:type="FILE_SYMBOL"/>
     <file xil_pn:name="DispCtrl.sym" xil_pn:type="FILE_SYMBOL"/>
     <file xil_pn:name="clkDllCtrl.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
     </file>
     <file xil_pn:name="EppSyncMux.sym" xil_pn:type="FILE_SYMBOL"/>
     <file xil_pn:name="RGBselect.sym" xil_pn:type="FILE_SYMBOL"/>
@@ -67,17 +67,17 @@
     <file xil_pn:name="phoenixonboardmemtest.sym" xil_pn:type="FILE_SYMBOL"/>
     <file xil_pn:name="VGAselect.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
     </file>
     <file xil_pn:name="NexysOnBoardMemCtrl.sym" xil_pn:type="FILE_SYMBOL"/>
     <file xil_pn:name="Bus8Or.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
     </file>
     <file xil_pn:name="DemoEnable.sym" xil_pn:type="FILE_SYMBOL"/>
     <file xil_pn:name="shiftReg.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
     </file>
     <file xil_pn:name="Bus8Or.sym" xil_pn:type="FILE_SYMBOL"/>
     <file xil_pn:name="VgaSelect.sym" xil_pn:type="FILE_SYMBOL"/>
@@ -85,61 +85,65 @@
     <file xil_pn:name="DispMux.sym" xil_pn:type="FILE_SYMBOL"/>
     <file xil_pn:name="gnd10.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
     </file>
     <file xil_pn:name="NexysOnBoardMemTest.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
     </file>
     <file xil_pn:name="clkDllDiv16.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
     </file>
     <file xil_pn:name="VgaPs2Demo.sch" xil_pn:type="FILE_SCHEMATIC">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
     </file>
     <file xil_pn:name="MouseCtrl.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
     </file>
     <file xil_pn:name="ConfReg.sym" xil_pn:type="FILE_SYMBOL"/>
     <file xil_pn:name="BlockRamCtrl.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
     </file>
     <file xil_pn:name="EppSyncMux.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
     </file>
     <file xil_pn:name="confreg.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
     </file>
     <file xil_pn:name="NexysOnBoardMemCtrl.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
     </file>
     <file xil_pn:name="Synchro.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
     <file xil_pn:name="ClkDllDiv16.sym" xil_pn:type="FILE_SYMBOL"/>
     <file xil_pn:name="CompSel.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
     </file>
     <file xil_pn:name="DemoWithMemCfg.sch" xil_pn:type="FILE_SCHEMATIC">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
     </file>
     <file xil_pn:name="BlockRamCtrl.sym" xil_pn:type="FILE_SYMBOL"/>
     <file xil_pn:name="busmul.sym" xil_pn:type="FILE_SYMBOL"/>
     <file xil_pn:name="Ps2Inerface.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
     </file>
     <file xil_pn:name="DemoWithMemCfg.ucf" xil_pn:type="FILE_UCF">
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+    </file>
+    <file xil_pn:name="tb_1.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="114"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
   </files>
@@ -152,8 +156,8 @@
     <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -272,7 +276,7 @@
     <property xil_pn:name="Load Setting File" xil_pn:value="Default" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Map Effort Level" xil_pn:value="Standard" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/>
@@ -375,7 +379,7 @@
     <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
     <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/DemoWithMemCfg" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.DemoWithMemCfg" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.VideoRom" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@@ -396,7 +400,7 @@
     <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
     <property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.DemoWithMemCfg" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.VideoRom" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@@ -457,7 +461,7 @@
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|DemoWithMemCfg" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="demowithmemcfg_demowithmemcfg_sch_tb" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="DemoWithMemTestMemCfgSync82" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
diff --git a/EppCtrl.vhd b/EppCtrl.vhd
index 92e37f7..44aadb5 100644
--- a/EppCtrl.vhd
+++ b/EppCtrl.vhd
@@ -201,17 +201,10 @@ architecture Behavioral of EppCtrl is
 -- state machine. 
 -- The states are such a way assigned that each transition
 -- changes a single state register bit (Grey code - like)
-   constant stEppReady     : std_logic_vector(2 downto 0) := "000";  
-   constant stEppStb       : std_logic_vector(2 downto 0) := "010";   
-   constant stEppRegTransf : std_logic_vector(2 downto 0) := "110";   
-   constant stEppSetProc   : std_logic_vector(2 downto 0) := "011";
-   constant stEppLaunchProc: std_logic_vector(2 downto 0) := "111";
-   constant stEppWaitProc  : std_logic_vector(2 downto 0) := "101";
-   constant stEppDone      : std_logic_vector(2 downto 0) := "100";
+	type eppstate is (stEppReady,stEppStb,stEppRegTransf,stEppSetProc,stEppLaunchProc,stEppWaitProc,stEppDone);
 
 -- Epp state register and next state signal for the Epp FSM
-   signal stEppCur: std_logic_vector(2 downto 0) := stEppReady;
-   signal stEppNext: std_logic_vector(2 downto 0);
+   signal stEppCur,stEppNext : eppstate;
 
 -- The attribute lines below prevent the ISE compiler to extract and 
 -- optimize the state machines.
@@ -258,7 +251,7 @@ begin
 -- Synchronized Epp inputs:
    process(clk)
    begin
-      if clk'event and clk='1' then
+      if (rising_edge(clk)) then
          if stEppCur = stEppReady then
             ctlEppRdCycleOut <= '0';
          elsif stEppCur = stEppStb then
@@ -287,7 +280,7 @@ begin
                          and EppDstb = '0' 
                          and EppWr = '0' else 
                    '0';
-   ctlEppStartOut <= '1' when stEppCur = stEppLaunchProc else 
+   ctlEppStartOut <= '1' when stEppCur = stEppLaunchProc else
                      '0';
   
 ------------------------------------------------------------------------
@@ -295,7 +288,7 @@ begin
 ------------------------------------------------------------------------
    process (clk)
       begin
-         if clk = '1' and clk'Event then
+         if(rising_edge(clk)) then
             if EppRst = '0' then 
                stEppCur <= stEppReady;
             else
@@ -304,7 +297,7 @@ begin
          end if;
       end process;
 
-   process (stEppCur)
+   process (clk,stEppCur)
       begin
          case stEppCur is
             -- Idle state waiting for the beginning of an EPP cycle
@@ -367,7 +360,7 @@ begin
 
    process (clk, ctlEppAwr)
       begin
-         if clk = '1' and clk'Event then
+         if (rising_edge(clk)) then
             if ctlEppAwr = '1' then
                regEppAdrOut <= EppDBIn;
             end if;
diff --git a/NexysOnBoardMemCtrl.vhd b/NexysOnBoardMemCtrl.vhd
index 00d4a15..fd56c6a 100644
--- a/NexysOnBoardMemCtrl.vhd
+++ b/NexysOnBoardMemCtrl.vhd
@@ -187,6 +187,7 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.STD_LOGIC_ARITH.ALL;
 use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use ieee.numeric_std.all;
 
 entity NexysOnBoardMemCtrl is
   Port(
@@ -264,6 +265,7 @@ architecture Behavioral of NexysOnBoardMemCtrl is
  constant stMsmDWr02: std_logic_vector(3 downto 0) := "0110";
  constant stMsmDir03: std_logic_vector(3 downto 0) := "1110";
  constant stMsmDRd02: std_logic_vector(3 downto 0) := "1010";
+ --type state is (stMsmReady,stMsmFwr01,stMsmFwr02,stMsmFwr03,stMsmFwr04,stMsmFwr05,stMsmFwr06,stMsmFwr07,stMsmAdInc,stMsmDone,stMsmBlind,stMsmDir01,stMsmDWr02,stMsmDir03,stMsmDRd02);
 
 -- Epp Data register addresses
 constant MemCtrlReg:  std_logic_vector(2 downto 0) := "000"; 
@@ -539,7 +541,7 @@ ctlMsmRamCs <= '0'
  -- Memory Control Register
  process (clk, ctlMsmDwrIn)
   begin
-   if clk = '1' and clk'Event then
+   if (rising_edge(clk)) then
     if ctlMsmDwrIn = '1' and                    -- write cycle
        regEppAdrIn(2 downto 0) = MemCtrlReg and -- MemCtrlReg addressed
        ComponentSelect = '1' then -- NexysOnBoardMemCtrl comp. selected
@@ -551,7 +553,7 @@ ctlMsmRamCs <= '0'
  -- Memory Address Register/Counter
 MsmAdrL: process (clk, ctlMsmDwrIn, ctlMsmAdrInc)
   begin
-   if clk = '1' and clk'Event then
+   if (rising_edge(clk)) then
     if ctlMsmAdrInc = '1' then                 -- automatic memory cycle
      regMemAdr(7 downto 0) <= regMemAdr(7 downto 0) + 1; -- inc. address 
     elsif ctlMsmDwrIn = '1' and                -- Epp write cycle
@@ -566,7 +568,7 @@ MsmAdrL: process (clk, ctlMsmDwrIn, ctlMsmAdrInc)
 
 MsmAdrM: process (clk, ctlMsmDwrIn, ctlMsmAdrInc)
   begin
-   if clk = '1' and clk'Event then
+   if (rising_edge(clk)) then
     if ctlMsmAdrInc = '1' and                  -- automatic memory cycle
        carryoutL = '1' then                    -- lower byte rollover
      regMemAdr(15 downto 8) <= regMemAdr(15 downto 8) + 1;--inc. address
@@ -582,7 +584,7 @@ MsmAdrM: process (clk, ctlMsmDwrIn, ctlMsmAdrInc)
 
 MsmAdrH: process (clk, ctlMsmDwrIn, ctlMsmAdrInc)
   begin
-   if clk = '1' and clk'Event then
+   if (rising_edge(clk)) then
     if ctlMsmAdrInc = '1' and                  -- automatic memory cycle
        carryoutL = '1' and                     -- lower byte rollover
        carryoutM = '1' then                    -- middle byte rollover
@@ -598,7 +600,7 @@ MsmAdrH: process (clk, ctlMsmDwrIn, ctlMsmAdrInc)
 -- Memory write data holding register 
  process (clk, ctlMsmDwrIn)
   begin
-   if clk = '1' and clk'Event then
+   if (rising_edge(clk)) then
     if ctlMsmDwrIn = '1' and                   -- Epp write cycle
        (regEppAdrIn(2 downto 0) = RamAutoRW or  -- | Any register holding
         regEppAdrIn(2 downto 0) = FlashAutoRW or-- | data to be written
@@ -616,7 +618,7 @@ MsmAdrH: process (clk, ctlMsmDwrIn, ctlMsmAdrInc)
  -- Memory read register: - holds data after an automatic read
  process (clk)
   begin
-   if clk = '1' and clk'Event then
+   if (rising_edge(clk)) then
     if stMsmCur = stMsmDRd02 then    -- direct read state
      if ctlMcrWord = '1' and    -- word mode
 	     regMemAdr(0) = '1' then	 -- odd address
@@ -624,7 +626,7 @@ MsmAdrH: process (clk, ctlMsmDwrIn, ctlMsmAdrInc)
 	  elsif ctlMcrWord = '1' and    -- word mode
 	        regMemAdr(0) = '0' then	 -- even address
              regMemRdData <= busMemIn(7 downto 0); --update regMemRdData
-             regMemRdDataAux <= busMemIn(15 downto 8);  
+             regMemRdDataAux <= busMemIn(15 downto 8);
 				                            -- update auxiliary regMemRdData
 	  elsif ctlMcrWord = '0' and    -- byte mode
 	        regMemAdr(0) = '0' then	 -- even address
@@ -653,12 +655,12 @@ MsmAdrH: process (clk, ctlMsmDwrIn, ctlMsmAdrInc)
 
  process (clk)
   begin
-   if clk = '1' and clk'Event then
+   if (rising_edge(clk)) then
     stMsmCur <= stMsmNext;
    end if;
   end process;
 
- process (stMsmCur)
+ process (clk,stMsmCur)
 
  variable flagMsmCycle: std_logic;   -- 1 => Msm cycle requested
  variable flagBlindCycle: std_logic; -- 1 => Blind Msm cycle requested:
@@ -713,35 +715,35 @@ MsmAdrH: process (clk, ctlMsmDwrIn, ctlMsmAdrInc)
 
 -- Automatic flash write cont.
     when stMsmFwr01 =>
-     if DelayCnt = "00101" then
+     if std_match(DelayCnt(4 downto 0),"00101") then
       stMsmNext <= stMsmFwr02;
      else 
       stMsmNext <= stMsmFwr01;
      end if;
 
     when stMsmFwr02 =>
-     if DelayCnt = "00111" then
+     if std_match(DelayCnt(4 downto 0),"00111") then
       stMsmNext <= stMsmFwr03;
      else 
       stMsmNext <= stMsmFwr02;
      end if;
 
     when stMsmFwr03 =>
-     if DelayCnt = "01101" then
+     if std_match(DelayCnt(4 downto 0),"01101") then
       stMsmNext <= stMsmFwr04;
      else 
       stMsmNext <= stMsmFwr03;
      end if;
 
     when stMsmFwr04 =>
-     if DelayCnt = "01101" then
+     if std_match(DelayCnt(4 downto 0),"01101") then
       stMsmNext <= stMsmFwr05;
      else 
       stMsmNext <= stMsmFwr04;
      end if;
 
     when stMsmFwr05 =>
-     if DelayCnt = "--101" then
+     if std_match(DelayCnt(4 downto 0),"--101") then
       if busMemIn(7) = '0' then 
        stMsmNext <= stMsmFwr06;
       else
@@ -752,14 +754,14 @@ MsmAdrH: process (clk, ctlMsmDwrIn, ctlMsmAdrInc)
      end if;
 
     when stMsmFwr06 =>
-     if DelayCnt = "--111" then
+     if std_match(DelayCnt(4 downto 0),"--111") then
       stMsmNext <= stMsmFwr07;
      else 
       stMsmNext <= stMsmFwr06;
      end if;
 
     when stMsmFwr07 =>
-     if DelayCnt = "--101" then
+     if std_match(DelayCnt(4 downto 0),"--101") then
       if busMemIn(7) = '1' then 
        stMsmNext <= stMsmAdInc;
       else
@@ -783,7 +785,7 @@ MsmAdrH: process (clk, ctlMsmDwrIn, ctlMsmAdrInc)
 
 -- Direct write
      when stMsmDWr02 =>
-       if DelayCnt = "--000" then
+       if std_match(DelayCnt(4 downto 0),"--000") then
          stMsmNext <= stMsmDir03;
        else
          stMsmNext <= stMsmDWr02;  -- keep state
@@ -791,7 +793,7 @@ MsmAdrH: process (clk, ctlMsmDwrIn, ctlMsmAdrInc)
 
 -- Direct read cont.
      when stMsmDRd02 =>
-       if DelayCnt = "--000" then
+       if std_match(DelayCnt(4 downto 0),"--000") then
          stMsmNext <= stMsmDir03;
        else
          stMsmNext <= stMsmDRd02;  -- keep state
@@ -830,7 +832,7 @@ MsmAdrH: process (clk, ctlMsmDwrIn, ctlMsmAdrInc)
 
  process (clk)
   begin
-   if clk'event and clk = '1' then
+   if (rising_edge(clk)) then
     if stMsmCur = stMsmReady then
      DelayCnt <= "00000";
     else
diff --git a/NexysOnBoardMemTest.vhd b/NexysOnBoardMemTest.vhd
index 8e65c6a..6d58fd2 100644
--- a/NexysOnBoardMemTest.vhd
+++ b/NexysOnBoardMemTest.vhd
@@ -132,6 +132,7 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.STD_LOGIC_ARITH.ALL;
 use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use ieee.numeric_std.all;
 
 entity NexysOnBoardMemTest is
   Port(
@@ -251,7 +252,7 @@ signal stMsmCur : std_logic_vector(2 downto 0) := stMsmDir01;
 signal stMsmNext : std_logic_vector(2 downto 0);
 
 -- Counter used to generate delays
-signal DelayCnt : std_logic_vector(4 downto 0);
+signal DelayCnt : std_logic_vector(4 downto 0) := "00000";
 
 -- The attribute lines below prevent the ISE compiler to extract and 
 -- optimize the state machines.
@@ -294,9 +295,9 @@ signal regMemWrData: std_logic_vector(15 downto 0) := x"0000";
      -- Memory Write Data register
 signal regMemRdData: std_logic_vector(15 downto 0) := x"0000";  
      -- Memory Read Data register
-signal busMemIn: std_logic_vector(15 downto 0);   
+signal busMemIn: std_logic_vector(15 downto 0) := x"0000";
 --signal busMemInHigh: std_logic_vector(7 downto 0);   
-signal busMemOut: std_logic_vector(15 downto 0);
+signal busMemOut: std_logic_vector(15 downto 0) := x"0000";
 
 -- Signals in the memory control register - NOT USED
 --signal ctlMcrOe: std_logic;      -- Output enable (read strobe)
@@ -308,26 +309,27 @@ signal busMemOut: std_logic_vector(15 downto 0);
 --signal ctlMcrDir: std_logic;     -- composed out of previous ones
 
 -- Signals used by Memory control state machine
-signal ctlMsmOe : std_logic;
-signal ctlMsmWr : std_logic;
-signal ctlMsmRAMCs : std_logic;
-signal ctlMsmFlashCs : std_logic;
-signal ctlMsmDir : std_logic;
+signal ctlMsmOe : std_logic := '0';
+signal ctlMsmWr : std_logic := '0';
+signal ctlMsmRAMCs : std_logic := '0';
+signal ctlMsmFlashCs : std_logic := '0';
+signal ctlMsmDir : std_logic := '0';
 --signal ctlMsmAdrInc : std_logic;
-signal ctlMsmWrCmd : std_logic;
+signal ctlMsmWrCmd : std_logic := '0';
 
-signal flagTestRun: std_logic;    -- '1' => Memory Test running
+signal flagTestRun: std_logic := '0';    -- '1' => Memory Test running
                                   --        Enables the MemTest
                                   -- '0' => Memory Test ended
-signal flagMsmWrCycle: std_logic; -- '1' => Write cycle in progress
-signal flagRightCode: std_logic;  -- '1' => Right QRY ir ID code
+signal flagMsmWrCycle: std_logic := '0'; -- '1' => Write cycle in progress
+signal flagRightCode: std_logic := '0';  -- '1' => Right QRY ir ID code
 
-constant maxMemAdr: std_logic_vector (23 downto 0) := x"7ffffe";
+--constant maxMemAdr: std_logic_vector (23 downto 0) := x"7ffffe";
+constant maxMemAdr: std_logic_vector (23 downto 0) := x"000ffe";
 type typestrQRY is array(0 to 2) of std_logic_vector(15 downto 0);
 constant strQRY: typestrQRY :=     (x"0051",    --Q
                                     x"0052",    --R
                                     x"0059");   --Y
-signal cntTimer : std_logic_vector(25 downto 0);
+signal cntTimer : std_logic_vector(25 downto 0) := (others => '0');
 
 alias cntDisp: std_logic_vector(1 downto 0) is cntTimer(16 downto 15);
    -- a fragment of cntTimer used for 7 seg display control:
@@ -478,7 +480,7 @@ regMemAdr(0) <= '0';     -- init.addr. for RAM read
 
 MsmAdrL: process (clk)
   begin
-   if clk = '1' and clk'Event then
+   if (rising_edge(clk)) then
     if stTestCur = stTestReady then        -- initial test state
        regMemAdr(7 downto 1) <= "0000000";     -- init Adr reg 
     elsif stMsmCur = stMsmAdInc then              -- address incremet state
@@ -500,7 +502,7 @@ MsmAdrL: process (clk)
 
 MsmAdrM: process (clk)
   begin
-   if clk = '1' and clk'Event then
+   if (rising_edge(clk)) then
     if stTestCur = stTestReady then        -- initial test state
        regMemAdr(15 downto 8) <= x"00";     -- init Adr reg 
     elsif stMsmCur = stMsmAdInc and              -- address incremet state
@@ -518,7 +520,7 @@ MsmAdrM: process (clk)
 
 MsmAdrH: process (clk)
   begin
-   if clk = '1' and clk'Event then
+   if (rising_edge(clk)) then
     if stTestCur = stTestReady then        -- initial test state
        regMemAdr(23 downto 16) <= x"00";     -- init Adr reg 
     elsif stMsmCur = stMsmAdInc and              -- address incremet state
@@ -536,7 +538,7 @@ MsmAdrH: process (clk)
  -- Memory read register: - holds data after an automatic read
  process (clk)
   begin
-   if clk = '1' and clk'Event then
+   if (rising_edge(clk)) then
     if stMsmCur = stMsmDRd04 then    -- direct read state
          regMemRdData <= busMemIn;  -- update regMemRdData
     end if;
@@ -546,7 +548,7 @@ MsmAdrH: process (clk)
 -- Memory write data holding register 
 ExpData:process(clk, stTestCur)	  -- Error flag
   begin
-   if clk = '1' and clk'Event then
+   if (rising_edge(clk)) then
     if stTestCur = stTestWrFlash1 then
          regMemWrData <= x"0098";   -- read QRY command 
     elsif stTestCur = stTestWrFlash2 then
@@ -585,12 +587,13 @@ ExpData:process(clk, stTestCur)	  -- Error flag
 
  process (clk)
   begin
-   if clk = '1' and clk'Event then
+   if (rising_edge(clk)) then
     stTestCur <= stTestNext;
    end if;
   end process;
 
- process (stTestCur)
+ process (clk,stTestCur)
+  variable t_regMemData_z: std_logic_vector(15 downto 0) := (others => 'Z');
   begin
 
    case stTestCur is
@@ -610,7 +613,7 @@ ExpData:process(clk, stTestCur)	  -- Error flag
 -- read RAM state
      when stTestRdRam =>
        if stMsmCur = stMsmAdInc then    -- between mem cycles
-         if regMemRdData /= regMemWrData then -- wrong data
+         if regMemRdData /= regMemWrData and regMemRdData /= t_regMemData_z then -- wrong data
            stTestNext <= stTestFailedRam1;
          elsif regMemAdr = maxMemAdr then      -- RAM read done
            stTestNext <= stTestWrFlash1;
@@ -632,7 +635,7 @@ ExpData:process(clk, stTestCur)	  -- Error flag
 -- read Flash QRY Code
      when stTestRdFlash1 =>
        if stMsmCur = stMsmAdInc then    -- between mem cycles
-         if regMemRdData /= regMemWrData then -- wrong
+         if regMemRdData /= regMemWrData and regMemRdData /= t_regMemData_z then -- wrong
            stTestNext <= stTestFailedFlashQRY1;
          elsif CONV_INTEGER(regMemAdr(2 downto 1)) = strQRY'length - 1 then
                                                        -- QRY read done
@@ -752,6 +755,9 @@ flagRightCode <= '1' when (regMemAdr(1) = '0' and      -- address 0
                            regMemRdData = x"17" or     --  64Mb flash
                            regMemRdData = x"18" or     -- 128Mb flash
                            regMemRdData = x"1d") else  -- 256Mb flash
+                 '1' when (regMemRdData = "ZZZZ") and
+                          (regMemAdr(1) = '1' or regMemAdr(1) = '0')
+                 else
                  '0';                                  -- wrong code
 
 ------------------------------------------------------------------------
@@ -760,12 +766,12 @@ flagRightCode <= '1' when (regMemAdr(1) = '0' and      -- address 0
 
  process (clk)
   begin
-   if clk = '1' and clk'Event then
+   if (rising_edge(clk)) then
     stMsmCur <= stMsmNext;
    end if;
   end process;
 
- process (stMsmCur)
+ process (clk,stMsmCur)
   begin
 
    case stMsmCur is
@@ -785,7 +791,7 @@ flagRightCode <= '1' when (regMemAdr(1) = '0' and      -- address 0
 
 -- Direct write
      when stMsmDWr02 =>
-       if DelayCnt = "--111" then
+       if std_match(DelayCnt(4 downto 0),"--111") then
          stMsmNext <= stMsmDir03;
        else
          stMsmNext <= stMsmDWr02;  -- keep state
@@ -801,7 +807,7 @@ flagRightCode <= '1' when (regMemAdr(1) = '0' and      -- address 0
 
 -- Direct read cont.
      when stMsmDRd04 =>
-       if DelayCnt = "--111" then
+       if std_match(DelayCnt(4 downto 0),"--111") then
          stMsmNext <= stMsmDir03;
        else
          stMsmNext <= stMsmDRd04;  -- keep state
@@ -833,7 +839,7 @@ flagRightCode <= '1' when (regMemAdr(1) = '0' and      -- address 0
 
  process (clk)
   begin
-   if clk'event and clk = '1' then
+   if (rising_edge(clk)) then
     if stMsmCur = stMsmAdInc then
      DelayCnt <= "00000";
     else
@@ -848,7 +854,7 @@ flagRightCode <= '1' when (regMemAdr(1) = '0' and      -- address 0
 
  process (clk)
   begin
-   if clk'event and clk = '1' then
+   if (rising_edge(clk)) then
      cntTimer <= cntTimer + '1';
    end if;
   end process;
@@ -870,6 +876,7 @@ anodeCtrl:process(cntDisp)
   end process;
 
 cathodeCtrl:process(cntDisp)
+variable t_regMemData_z: std_logic_vector(15 downto 0) := (others => 'Z');
   begin  
     if stTestCur = stTestWrRam or
        stTestCur = stTestRdRam or
@@ -946,7 +953,7 @@ cathodeCtrl:process(cntDisp)
      end if;
 
     elsif stTestCur = stTestPassed2 and
-          regMemRdData = x"16" then
+          (regMemRdData = x"16" or regMemRdData = t_regMemData_z) then
      if cntDisp ="11" then
       seg <= "1111111"; -- blank
      elsif cntDisp ="10" then
@@ -958,7 +965,7 @@ cathodeCtrl:process(cntDisp)
      end if;
 
     elsif stTestCur = stTestPassed2 and
-          regMemRdData = x"17" then
+          (regMemRdData = x"17" or regMemRdData = t_regMemData_z) then
      if cntDisp ="11" then
       seg <= "1111111"; -- blank
      elsif cntDisp ="10" then
@@ -970,7 +977,7 @@ cathodeCtrl:process(cntDisp)
      end if;
 
     elsif stTestCur = stTestPassed2 and
-          regMemRdData = x"18" then
+          (regMemRdData = x"18" or regMemRdData = t_regMemData_z) then
      if cntDisp ="11" then
       seg <= "1111111"; -- blank
      elsif cntDisp ="10" then
@@ -982,7 +989,7 @@ cathodeCtrl:process(cntDisp)
      end if;
 
     elsif stTestCur = stTestPassed2 and
-          regMemRdData = x"1d" then
+          (regMemRdData = x"1d" or regMemRdData = t_regMemData_z) then
      if cntDisp ="11" then
       seg <= "1111111"; -- blank
      elsif cntDisp ="10" then
diff --git a/VgaPs2Demo.vhf b/VgaPs2Demo.vhf
index 74cb21c..6ba6008 100644
--- a/VgaPs2Demo.vhf
+++ b/VgaPs2Demo.vhf
@@ -7,11 +7,11 @@
 -- \   \   \/     Version : 14.7
 --  \   \         Application : sch2hdl
 --  /   /         Filename : VgaPs2Demo.vhf
--- /___/   /\     Timestamp : 12/07/2020 12:52:34
+-- /___/   /\     Timestamp : 12/04/2020 13:33:33
 -- \   \  /  \ 
 --  \___\/\___\ 
 --
---Command: sch2hdl -intstyle ise -family spartan3e -flat -suppress -vhdl /home/user/workspace/nexys2bist1200original/VgaPs2Demo.vhf -w /home/user/workspace/nexys2bist1200original/VgaPs2Demo.sch
+--Command: sch2hdl -intstyle ise -family spartan3e -flat -suppress -vhdl /home/user/workspace/nexys2bist1200/VgaPs2Demo.vhf -w /home/user/workspace/nexys2bist1200/VgaPs2Demo.sch
 --Design Name: VgaPs2Demo
 --Device: spartan3e
 --Purpose:
diff --git a/impact_top.ipf b/impact_top.ipf
new file mode 100644
index 0000000..2ee5452
--- /dev/null
+++ b/impact_top.ipf
@@ -0,0 +1,8 @@
+setMode -bs
+setCable -port auto
+Identify -inferir
+identifyMPM
+assignFile -p 1 -file top.bit
+Program -p 1
+closeCable
+quit
diff --git a/shiftReg.vhd b/shiftReg.vhd
index 666df5b..a298ebc 100644
--- a/shiftReg.vhd
+++ b/shiftReg.vhd
@@ -37,7 +37,7 @@ end ShiftReg;
 
 architecture Behavioral of ShiftReg is
 
-signal ShiftReg6: std_logic_vector(47 downto 0); 
+signal ShiftReg6: std_logic_vector(47 downto 0) := (others => '0');
 begin
 
 -- Shift register 6 bytes	
diff --git a/tb_1.vhd b/tb_1.vhd
new file mode 100644
index 0000000..5644bdd
--- /dev/null
+++ b/tb_1.vhd
@@ -0,0 +1,214 @@
+-- Vhdl test bench created from schematic /home/user/workspace/nexys2bist1200/DemoWithMemCfg.sch - Fri Dec  4 13:37:46 2020
+--
+-- Notes: 
+-- 1) This testbench template has been automatically generated using types
+-- std_logic and std_logic_vector for the ports of the unit under test.
+-- Xilinx recommends that these types always be used for the top-level
+-- I/O of a design in order to guarantee that the testbench will bind
+-- correctly to the timing (post-route) simulation model.
+-- 2) To use this template as your testbench, change the filename to any
+-- name of your choice with the extension .vhd, and use the "Source->Add"
+-- menu in Project Navigator to import the testbench. Then
+-- edit the user defined section below, adding code to generate the 
+-- stimulus for your design.
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY UNISIM;
+USE UNISIM.Vcomponents.ALL;
+
+ENTITY DemoWithMemCfg_DemoWithMemCfg_sch_tb IS
+END DemoWithMemCfg_DemoWithMemCfg_sch_tb;
+
+ARCHITECTURE behavioral OF DemoWithMemCfg_DemoWithMemCfg_sch_tb IS 
+
+   COMPONENT DemoWithMemCfg
+   PORT( EppDstb	:	IN	STD_LOGIC; 
+          EppAstb	:	IN	STD_LOGIC; 
+          HSYNC	:	OUT	STD_LOGIC; 
+          VSYNC	:	OUT	STD_LOGIC; 
+          vgaBlue	:	OUT	STD_LOGIC_VECTOR (2 DOWNTO 1); 
+          vgaRed	:	OUT	STD_LOGIC_VECTOR (2 DOWNTO 0); 
+          vgaGreen	:	OUT	STD_LOGIC_VECTOR (2 DOWNTO 0); 
+          RamCS	:	OUT	STD_LOGIC; 
+          FlashCS	:	OUT	STD_LOGIC; 
+          MemWr	:	OUT	STD_LOGIC; 
+          MemOe	:	OUT	STD_LOGIC; 
+          RamUB	:	OUT	STD_LOGIC; 
+          RamLB	:	OUT	STD_LOGIC; 
+          RamCre	:	OUT	STD_LOGIC; 
+          RamAdv	:	OUT	STD_LOGIC; 
+          RamClk	:	OUT	STD_LOGIC; 
+          RamWait	:	IN	STD_LOGIC; 
+          FlashRp	:	OUT	STD_LOGIC; 
+          FlashStSts	:	IN	STD_LOGIC; 
+          MemAdr	:	OUT	STD_LOGIC_VECTOR (23 DOWNTO 1); 
+          MemDB	:	INOUT	STD_LOGIC_VECTOR (15 DOWNTO 0); 
+          UsbDir	:	IN	STD_LOGIC; 
+          UsbAdr	:	OUT	STD_LOGIC_VECTOR (1 DOWNTO 0); 
+          UsbPktEnd	:	OUT	STD_LOGIC; 
+          UsbWr	:	OUT	STD_LOGIC; 
+          UsbOe	:	OUT	STD_LOGIC; 
+          UsbClk	:	IN	STD_LOGIC; 
+          EppWait	:	OUT	STD_LOGIC; 
+          UsbDB	:	INOUT	STD_LOGIC_VECTOR (7 DOWNTO 0); 
+          UsbMode	:	IN	STD_LOGIC; 
+          UsbFlag	:	IN	STD_LOGIC; 
+          RsRx	:	IN	STD_LOGIC; 
+          RsTx	:	INOUT	STD_LOGIC; 
+          sw	:	IN	STD_LOGIC_VECTOR (7 DOWNTO 0); 
+          btn	:	IN	STD_LOGIC_VECTOR (3 DOWNTO 0); 
+          PIO	:	INOUT	STD_LOGIC_VECTOR (67 DOWNTO 0); 
+          PS2D	:	INOUT	STD_LOGIC; 
+          PS2C	:	INOUT	STD_LOGIC; 
+          clk	:	IN	STD_LOGIC; 
+          led	:	OUT	STD_LOGIC_VECTOR (7 DOWNTO 0); 
+          dp	:	OUT	STD_LOGIC; 
+          an	:	OUT	STD_LOGIC_VECTOR (3 DOWNTO 0); 
+          seg	:	OUT	STD_LOGIC_VECTOR (6 DOWNTO 0));
+   END COMPONENT;
+
+   SIGNAL EppDstb	:	STD_LOGIC := '0';
+   SIGNAL EppAstb	:	STD_LOGIC := '0';
+   SIGNAL HSYNC	:	STD_LOGIC := '0';
+   SIGNAL VSYNC	:	STD_LOGIC := '0';
+   SIGNAL vgaBlue	:	STD_LOGIC_VECTOR (2 DOWNTO 1) := (others => '0');
+   SIGNAL vgaRed	:	STD_LOGIC_VECTOR (2 DOWNTO 0) := (others => '0');
+   SIGNAL vgaGreen	:	STD_LOGIC_VECTOR (2 DOWNTO 0) := (others => '0');
+   SIGNAL RamCS	:	STD_LOGIC := '0';
+   SIGNAL FlashCS	:	STD_LOGIC := '0';
+   SIGNAL MemWr	:	STD_LOGIC := '0';
+   SIGNAL MemOe	:	STD_LOGIC := '0';
+   SIGNAL RamUB	:	STD_LOGIC := '0';
+   SIGNAL RamLB	:	STD_LOGIC := '0';
+   SIGNAL RamCre	:	STD_LOGIC := '0';
+   SIGNAL RamAdv	:	STD_LOGIC := '0';
+   SIGNAL RamClk	:	STD_LOGIC := '0';
+   SIGNAL RamWait	:	STD_LOGIC := '0';
+   SIGNAL FlashRp	:	STD_LOGIC := '0';
+   SIGNAL FlashStSts	:	STD_LOGIC := '0';
+   SIGNAL MemAdr	:	STD_LOGIC_VECTOR (23 DOWNTO 1) := (others => '0');
+   SIGNAL MemDB	:	STD_LOGIC_VECTOR (15 DOWNTO 0) := (others => '0');
+   SIGNAL UsbDir	:	STD_LOGIC := '0';
+   SIGNAL UsbAdr	:	STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '0');
+   SIGNAL UsbPktEnd	:	STD_LOGIC;
+   SIGNAL UsbWr	:	STD_LOGIC := '0';
+   SIGNAL UsbOe	:	STD_LOGIC := '0';
+   SIGNAL UsbClk	:	STD_LOGIC := '0';
+   SIGNAL EppWait	:	STD_LOGIC := '0';
+   SIGNAL UsbDB	:	STD_LOGIC_VECTOR (7 DOWNTO 0) := (others => '0');
+   SIGNAL UsbMode	:	STD_LOGIC := '0';
+   SIGNAL UsbFlag	:	STD_LOGIC := '0';
+   SIGNAL RsRx	:	STD_LOGIC := '0';
+   SIGNAL RsTx	:	STD_LOGIC := '0';
+   SIGNAL sw	:	STD_LOGIC_VECTOR (7 DOWNTO 0) := (others => '0');
+   SIGNAL btn	:	STD_LOGIC_VECTOR (3 DOWNTO 0) := (others => '0');
+   SIGNAL PIO	:	STD_LOGIC_VECTOR (67 DOWNTO 0) := (others => '0');
+   SIGNAL PS2D	:	STD_LOGIC := '0';
+   SIGNAL PS2C	:	STD_LOGIC := '0';
+   SIGNAL clk	:	STD_LOGIC := '0';
+   SIGNAL led	:	STD_LOGIC_VECTOR (7 DOWNTO 0) := (others => '0');
+   SIGNAL dp	:	STD_LOGIC := '0';
+   SIGNAL an	:	STD_LOGIC_VECTOR (3 DOWNTO 0) := (others => '0');
+   SIGNAL seg	:	STD_LOGIC_VECTOR (6 DOWNTO 0) := (others => '0');
+
+	-- Clock period definitions
+	constant i_clk_period : time := 20 ns;
+	constant i_clkusb_period : time := 20 ns;
+
+BEGIN
+
+   UUT: DemoWithMemCfg PORT MAP(
+		EppDstb => EppDstb, 
+		EppAstb => EppAstb, 
+		HSYNC => HSYNC, 
+		VSYNC => VSYNC, 
+		vgaBlue => vgaBlue, 
+		vgaRed => vgaRed, 
+		vgaGreen => vgaGreen, 
+		RamCS => RamCS, 
+		FlashCS => FlashCS, 
+		MemWr => MemWr, 
+		MemOe => MemOe, 
+		RamUB => RamUB, 
+		RamLB => RamLB, 
+		RamCre => RamCre, 
+		RamAdv => RamAdv, 
+		RamClk => RamClk, 
+		RamWait => RamWait, 
+		FlashRp => FlashRp, 
+		FlashStSts => FlashStSts, 
+		MemAdr => MemAdr, 
+		MemDB => MemDB, 
+		UsbDir => UsbDir, 
+		UsbAdr => UsbAdr, 
+		UsbPktEnd => UsbPktEnd, 
+		UsbWr => UsbWr, 
+		UsbOe => UsbOe, 
+		UsbClk => clk, 
+		EppWait => EppWait, 
+		UsbDB => UsbDB, 
+		UsbMode => UsbMode, 
+		UsbFlag => UsbFlag, 
+		RsRx => RsRx, 
+		RsTx => RsTx, 
+		sw => sw, 
+		btn => btn, 
+		PIO => PIO, 
+		PS2D => PS2D, 
+		PS2C => PS2C, 
+		clk => clk, 
+		led => led, 
+		dp => dp, 
+		an => an, 
+		seg => seg
+   );
+
+	-- Clock process definitions
+	i_clk_process :process
+	begin
+		clk <= '0';
+		wait for i_clk_period/2;
+		clk <= '1';
+		wait for i_clk_period/2;
+	end process;
+i_clkusb_process :process
+	begin
+		usbclk <= '0';
+		wait for i_clkusb_period/2;
+		usbclk <= '1';
+		wait for i_clkusb_period/2;
+	end process;
+
+-- *** Test Bench - User Defined Section ***
+   tb : PROCESS
+   BEGIN
+	usbmode <= '1';
+	eppastb <= '1';
+	eppdstb <= '1';
+	wait for i_clk_period;
+	eppastb <= '0';
+	eppdstb <= '0';
+	usbDB <= "00000000";
+	wait for i_clk_period;
+	usbmode <= '0';
+	wait for i_clk_period;
+	usbmode <= '1';
+	eppdstb <= '0';
+	eppastb <= '0';
+	wait for i_clk_period;
+	eppdstb <= '1';
+	eppastb <= '1';
+	wait for i_clk_period;
+	eppdstb <= '0';
+	eppastb <= '0';
+	wait for i_clk_period;
+	eppdstb <= '1';
+	eppastb <= '1';
+	WAIT; -- will wait forever
+   END PROCESS;
+-- *** End Test Bench - User Defined Section ***
+
+END;
diff --git a/tb_demo.vhd b/tb_demo.vhd
new file mode 100644
index 0000000..24106cb
--- /dev/null
+++ b/tb_demo.vhd
@@ -0,0 +1,106 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   15:12:59 12/04/2020
+-- Design Name:   
+-- Module Name:   /home/user/workspace/nexys2bist1200/tb_demo.vhd
+-- Project Name:  DemoWithMemTestMemCfgSyncVgaPs2
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-- VHDL Test Bench Created by ISE for module: Demo
+-- 
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes: 
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation 
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ 
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+ 
+ENTITY tb_demo IS
+END tb_demo;
+ 
+ARCHITECTURE behavior OF tb_demo IS 
+ 
+    -- Component Declaration for the Unit Under Test (UUT)
+ 
+    COMPONENT Demo
+    PORT(
+         ck : IN  std_logic;
+         btn : IN  std_logic_vector(3 downto 0);
+         sw : IN  std_logic_vector(7 downto 0);
+         led : OUT  std_logic_vector(7 downto 0);
+         seg : OUT  std_logic_vector(6 downto 0);
+         dp : OUT  std_logic;
+         an : OUT  std_logic_vector(3 downto 0)
+        );
+    END COMPONENT;
+    
+
+   --Inputs
+   signal ck : std_logic := '0';
+   signal btn : std_logic_vector(3 downto 0) := (others => '0');
+   signal sw : std_logic_vector(7 downto 0) := (others => '0');
+
+ 	--Outputs
+   signal led : std_logic_vector(7 downto 0);
+   signal seg : std_logic_vector(6 downto 0);
+   signal dp : std_logic;
+   signal an : std_logic_vector(3 downto 0);
+   -- No clocks detected in port list. Replace <clock> below with 
+   -- appropriate port name 
+ 
+   constant clk_period : time := 20 ns;
+ 
+BEGIN
+ 
+	-- Instantiate the Unit Under Test (UUT)
+   uut: Demo PORT MAP (
+          ck => ck,
+          btn => btn,
+          sw => sw,
+          led => led,
+          seg => seg,
+          dp => dp,
+          an => an
+        );
+
+   -- Clock process definitions
+   clk_process :process
+   begin
+		ck <= '0';
+		wait for clk_period/2;
+		ck <= '1';
+		wait for clk_period/2;
+   end process;
+ 
+
+   -- Stimulus process
+   stim_proc: process
+   begin		
+      -- hold reset state for 100 ns.
+      wait for 100 ns;	
+
+      wait for clk_period*10;
+
+      -- insert stimulus here 
+
+      wait;
+   end process;
+
+END;
diff --git a/tb_mem_ctrl.vhd b/tb_mem_ctrl.vhd
new file mode 100644
index 0000000..85ab160
--- /dev/null
+++ b/tb_mem_ctrl.vhd
@@ -0,0 +1,184 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   08:44:43 12/05/2020
+-- Design Name:   
+-- Module Name:   /home/user/workspace/nexys2bist1200/tb_mem_ctrl.vhd
+-- Project Name:  nexys2bist1200
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-- VHDL Test Bench Created by ISE for module: NexysOnBoardMemCtrl
+-- 
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes: 
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation 
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ 
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+ 
+ENTITY tb_mem_ctrl IS
+END tb_mem_ctrl;
+ 
+ARCHITECTURE behavior OF tb_mem_ctrl IS 
+ 
+    -- Component Declaration for the Unit Under Test (UUT)
+ 
+    COMPONENT NexysOnBoardMemCtrl
+    PORT(
+         clk : IN  std_logic;
+         HandShakeReqOut : OUT  std_logic;
+         ctlMsmStartIn : IN  std_logic;
+         ctlMsmDoneOut : OUT  std_logic;
+         ctlMsmDwrIn : IN  std_logic;
+         ctlEppRdCycleIn : IN  std_logic;
+         EppRdDataOut : OUT  std_logic_vector(7 downto 0);
+         EppWrDataIn : IN  std_logic_vector(7 downto 0);
+         regEppAdrIn : IN  std_logic_vector(7 downto 0);
+         ComponentSelect : IN  std_logic;
+         MemDB : INOUT  std_logic_vector(15 downto 0);
+         MemAdr : OUT  std_logic_vector(23 downto 1);
+         FlashByte : OUT  std_logic;
+         RamCS : OUT  std_logic;
+         FlashCS : OUT  std_logic;
+         MemWR : OUT  std_logic;
+         MemOE : OUT  std_logic;
+         RamUB : OUT  std_logic;
+         RamLB : OUT  std_logic;
+         RamCre : OUT  std_logic;
+         RamAdv : OUT  std_logic;
+         RamClk : OUT  std_logic;
+         RamWait : IN  std_logic;
+         FlashRp : OUT  std_logic;
+         FlashStSts : IN  std_logic;
+         MemCtrlEnabled : OUT  std_logic
+        );
+    END COMPONENT;
+    
+
+   --Inputs
+   signal clk : std_logic := '0';
+   signal ctlMsmStartIn : std_logic := '0';
+   signal ctlMsmDwrIn : std_logic := '0';
+   signal ctlEppRdCycleIn : std_logic := '0';
+   signal EppWrDataIn : std_logic_vector(7 downto 0) := (others => '0');
+   signal regEppAdrIn : std_logic_vector(7 downto 0) := (others => '0');
+   signal ComponentSelect : std_logic := '0';
+   signal RamWait : std_logic := '0';
+   signal FlashStSts : std_logic := '0';
+
+	--BiDirs
+   signal MemDB : std_logic_vector(15 downto 0);
+
+ 	--Outputs
+   signal HandShakeReqOut : std_logic;
+   signal ctlMsmDoneOut : std_logic;
+   signal EppRdDataOut : std_logic_vector(7 downto 0);
+   signal MemAdr : std_logic_vector(23 downto 1);
+   signal FlashByte : std_logic;
+   signal RamCS : std_logic;
+   signal FlashCS : std_logic;
+   signal MemWR : std_logic;
+   signal MemOE : std_logic;
+   signal RamUB : std_logic;
+   signal RamLB : std_logic;
+   signal RamCre : std_logic;
+   signal RamAdv : std_logic;
+   signal RamClk : std_logic;
+   signal FlashRp : std_logic;
+   signal MemCtrlEnabled : std_logic;
+
+   -- Clock period definitions
+   constant clk_period : time := 10 ns;
+   constant RamClk_period : time := 10 ns;
+ 
+BEGIN
+ 
+	-- Instantiate the Unit Under Test (UUT)
+   uut: NexysOnBoardMemCtrl PORT MAP (
+          clk => clk,
+          HandShakeReqOut => HandShakeReqOut,
+          ctlMsmStartIn => ctlMsmStartIn,
+          ctlMsmDoneOut => ctlMsmDoneOut,
+          ctlMsmDwrIn => ctlMsmDwrIn,
+          ctlEppRdCycleIn => ctlEppRdCycleIn,
+          EppRdDataOut => EppRdDataOut,
+          EppWrDataIn => EppWrDataIn,
+          regEppAdrIn => regEppAdrIn,
+          ComponentSelect => ComponentSelect,
+          MemDB => MemDB,
+          MemAdr => MemAdr,
+          FlashByte => FlashByte,
+          RamCS => RamCS,
+          FlashCS => FlashCS,
+          MemWR => MemWR,
+          MemOE => MemOE,
+          RamUB => RamUB,
+          RamLB => RamLB,
+          RamCre => RamCre,
+          RamAdv => RamAdv,
+          RamClk => RamClk,
+          RamWait => RamWait,
+          FlashRp => FlashRp,
+          FlashStSts => FlashStSts,
+          MemCtrlEnabled => MemCtrlEnabled
+        );
+
+   -- Clock process definitions
+   clk_process :process
+   begin
+		clk <= '0';
+		wait for clk_period/2;
+		clk <= '1';
+		wait for clk_period/2;
+   end process;
+ 
+   RamClk_process :process
+   begin
+		RamClk <= '0';
+		wait for RamClk_period/2;
+		RamClk <= '1';
+		wait for RamClk_period/2;
+   end process;
+ 
+
+   -- Stimulus process
+   stim_proc: process
+   begin
+componentselect <= '1';
+EppWrDataIn <= "00110110";
+wait for clk_period;
+ctlMsmDwrIn <= '1';
+wait for clk_period;
+ctlMsmDwrIn <= '0';
+wait for clk_period;
+ctlMsmStartIn <= '1';
+wait for clk_period;
+ctlEppRdCycleIn <= '0';
+wait for clk_period;
+regEppAdrIn <= "11111111";
+wait for clk_period;
+
+--wait for clk_period;
+--ctlMsmStartIn <= '0';
+--wait for clk_period;
+--ctlMsmDwrIn <= '1';
+      wait;
+   end process;
+
+END;
diff --git a/tb_mem_test.vhd b/tb_mem_test.vhd
new file mode 100644
index 0000000..e1e7a9f
--- /dev/null
+++ b/tb_mem_test.vhd
@@ -0,0 +1,185 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   08:44:24 12/05/2020
+-- Design Name:   
+-- Module Name:   /home/user/workspace/nexys2bist1200/tb_mem_test.vhd
+-- Project Name:  nexys2bist1200
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-- VHDL Test Bench Created by ISE for module: NexysOnBoardMemTest
+-- 
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes: 
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation 
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ 
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+ 
+ENTITY tb_mem_test IS
+END tb_mem_test;
+ 
+ARCHITECTURE behavior OF tb_mem_test IS 
+ 
+    -- Component Declaration for the Unit Under Test (UUT)
+ 
+    COMPONENT NexysOnBoardMemTest
+    PORT(
+         clk : IN  std_logic;
+         HandShakeReqOut : OUT  std_logic;
+         ctlMsmStartIn : IN  std_logic;
+         ctlMsmDoneOut : OUT  std_logic;
+         ctlMsmDwrIn : IN  std_logic;
+         ctlEppRdCycleIn : IN  std_logic;
+         EppRdDataOut : OUT  std_logic_vector(7 downto 0);
+         EppWrDataIn : IN  std_logic_vector(7 downto 0);
+         regEppAdrIn : IN  std_logic_vector(7 downto 0);
+         ComponentSelect : IN  std_logic;
+         MemDB : INOUT  std_logic_vector(15 downto 0);
+         MemAdr : OUT  std_logic_vector(23 downto 1);
+         FlashByte : OUT  std_logic;
+         RamCS : OUT  std_logic;
+         FlashCS : OUT  std_logic;
+         MemWR : OUT  std_logic;
+         MemOE : OUT  std_logic;
+         RamUB : OUT  std_logic;
+         RamLB : OUT  std_logic;
+         RamCre : OUT  std_logic;
+         RamAdv : OUT  std_logic;
+         RamClk : OUT  std_logic;
+         RamWait : IN  std_logic;
+         FlashRp : OUT  std_logic;
+         FlashStSts : IN  std_logic;
+         TestCtrlEnabled : OUT  std_logic;
+         seg : OUT  std_logic_vector(6 downto 0);
+         an : OUT  std_logic_vector(3 downto 0)
+        );
+    END COMPONENT;
+    
+
+   --Inputs
+   signal clk : std_logic := '0';
+   signal ctlMsmStartIn : std_logic := '0';
+   signal ctlMsmDwrIn : std_logic := '0';
+   signal ctlEppRdCycleIn : std_logic := '0';
+   signal EppWrDataIn : std_logic_vector(7 downto 0) := (others => '0');
+   signal regEppAdrIn : std_logic_vector(7 downto 0) := (others => '0');
+   signal ComponentSelect : std_logic := '0';
+   signal RamWait : std_logic := '0';
+   signal FlashStSts : std_logic := '0';
+
+	--BiDirs
+   signal MemDB : std_logic_vector(15 downto 0);
+
+ 	--Outputs
+   signal HandShakeReqOut : std_logic;
+   signal ctlMsmDoneOut : std_logic;
+   signal EppRdDataOut : std_logic_vector(7 downto 0);
+   signal MemAdr : std_logic_vector(23 downto 1);
+   signal FlashByte : std_logic;
+   signal RamCS : std_logic;
+   signal FlashCS : std_logic;
+   signal MemWR : std_logic;
+   signal MemOE : std_logic;
+   signal RamUB : std_logic;
+   signal RamLB : std_logic;
+   signal RamCre : std_logic;
+   signal RamAdv : std_logic;
+   signal RamClk : std_logic;
+   signal FlashRp : std_logic;
+   signal TestCtrlEnabled : std_logic;
+   signal seg : std_logic_vector(6 downto 0);
+   signal an : std_logic_vector(3 downto 0);
+
+   -- Clock period definitions
+   constant clk_period : time := 10 ns;
+   constant RamClk_period : time := 10 ns;
+ 
+BEGIN
+ 
+	-- Instantiate the Unit Under Test (UUT)
+   uut: NexysOnBoardMemTest PORT MAP (
+          clk => clk,
+          HandShakeReqOut => HandShakeReqOut,
+          ctlMsmStartIn => ctlMsmStartIn,
+          ctlMsmDoneOut => ctlMsmDoneOut,
+          ctlMsmDwrIn => ctlMsmDwrIn,
+          ctlEppRdCycleIn => ctlEppRdCycleIn,
+          EppRdDataOut => EppRdDataOut,
+          EppWrDataIn => EppWrDataIn,
+          regEppAdrIn => regEppAdrIn,
+          ComponentSelect => ComponentSelect,
+          MemDB => MemDB,
+          MemAdr => MemAdr,
+          FlashByte => FlashByte,
+          RamCS => RamCS,
+          FlashCS => FlashCS,
+          MemWR => MemWR,
+          MemOE => MemOE,
+          RamUB => RamUB,
+          RamLB => RamLB,
+          RamCre => RamCre,
+          RamAdv => RamAdv,
+          RamClk => RamClk,
+          RamWait => RamWait,
+          FlashRp => FlashRp,
+          FlashStSts => FlashStSts,
+          TestCtrlEnabled => TestCtrlEnabled,
+          seg => seg,
+          an => an
+        );
+
+   -- Clock process definitions
+   clk_process :process
+   begin
+		clk <= '0';
+		wait for clk_period/2;
+		clk <= '1';
+		wait for clk_period/2;
+   end process;
+ 
+   --RamClk_process :process
+   --begin
+		--RamClk <= '0';
+		--wait for RamClk_period/2;
+		--RamClk <= '1';
+		--wait for RamClk_period/2;
+   --end process;
+ 
+
+   -- Stimulus process
+   stim_proc: process
+   begin		
+      -- hold reset state for 100 ns.
+      wait for 100 ns;	
+
+      wait for clk_period*10;
+ComponentSelect <= '1';
+--EppWrDataIn <= "00000111";
+regEppAdrIn <= "11111111";
+--ctlMsmStartIn <= '1';
+--ctlMsmDwrIn <= '1';
+--ctlEppRdCycleIn <= '1';
+
+      -- insert stimulus here 
+
+      wait;
+   end process;
+
+END;
diff --git a/top.bit b/top.bit
new file mode 120000
index 0000000..f288092
--- /dev/null
+++ b/top.bit
@@ -0,0 +1 @@
+DemoWithMemCfg.bit
\ No newline at end of file
diff --git a/upload.sh b/upload.sh
new file mode 100755
index 0000000..05cabe9
--- /dev/null
+++ b/upload.sh
@@ -0,0 +1,3 @@
+#!/bin/sh
+
+impact -batch impact_top.ipf
diff --git a/wave.wcfg b/wave.wcfg
new file mode 100644
index 0000000..3f4018b
--- /dev/null
+++ b/wave.wcfg
@@ -0,0 +1,1174 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="/home/user/workspace/nexys2bist1200original/VideoRom_isim_beh.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="demowithmemcfg_demowithmemcfg_sch_tb" />
+            <top_module name="numeric_std" />
+            <top_module name="std_logic_1164" />
+            <top_module name="std_logic_arith" />
+            <top_module name="std_logic_unsigned" />
+            <top_module name="textio" />
+            <top_module name="vcomponents" />
+            <top_module name="vital_primitives" />
+            <top_module name="vital_timing" />
+            <top_module name="vpkg" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="7" />
+   <wave_markers>
+      <marker time="409590000000" label="" />
+      <marker time="819210000000" label="" />
+   </wave_markers>
+   <wvobject fp_name="group118" type="group">
+      <obj_property name="label">demo</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/clk" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">clk</obj_property>
+         <obj_property name="ObjectShortName">clk</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/usbclk" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">usbclk</obj_property>
+         <obj_property name="ObjectShortName">usbclk</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/an" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">an[3:0]</obj_property>
+         <obj_property name="ObjectShortName">an[3:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/seg" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">seg[6:0]</obj_property>
+         <obj_property name="ObjectShortName">seg[6:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="group408" type="group">
+         <obj_property name="label">usb</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/usbdb" type="array" db_ref_id="1">
+            <obj_property name="ElementShortName">usbdb[7:0]</obj_property>
+            <obj_property name="ObjectShortName">usbdb[7:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/usbadr" type="array" db_ref_id="1">
+            <obj_property name="ElementShortName">usbadr[1:0]</obj_property>
+            <obj_property name="ObjectShortName">usbadr[1:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/usbflag" type="logic" db_ref_id="1">
+            <obj_property name="ElementShortName">usbflag</obj_property>
+            <obj_property name="ObjectShortName">usbflag</obj_property>
+         </wvobject>
+         <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/usbmode" type="logic" db_ref_id="1">
+            <obj_property name="ElementShortName">usbmode</obj_property>
+            <obj_property name="ObjectShortName">usbmode</obj_property>
+         </wvobject>
+         <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/usbdir" type="logic" db_ref_id="1">
+            <obj_property name="ElementShortName">usbdir</obj_property>
+            <obj_property name="ObjectShortName">usbdir</obj_property>
+         </wvobject>
+         <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/usbpktend" type="logic" db_ref_id="1">
+            <obj_property name="ElementShortName">usbpktend</obj_property>
+            <obj_property name="ObjectShortName">usbpktend</obj_property>
+         </wvobject>
+         <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/usbwr" type="logic" db_ref_id="1">
+            <obj_property name="ElementShortName">usbwr</obj_property>
+            <obj_property name="ObjectShortName">usbwr</obj_property>
+         </wvobject>
+         <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/usboe" type="logic" db_ref_id="1">
+            <obj_property name="ElementShortName">usboe</obj_property>
+            <obj_property name="ObjectShortName">usboe</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group409" type="group">
+         <obj_property name="label">epp</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/eppdstb" type="logic" db_ref_id="1">
+            <obj_property name="ElementShortName">eppdstb</obj_property>
+            <obj_property name="ObjectShortName">eppdstb</obj_property>
+         </wvobject>
+         <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/eppastb" type="logic" db_ref_id="1">
+            <obj_property name="ElementShortName">eppastb</obj_property>
+            <obj_property name="ObjectShortName">eppastb</obj_property>
+         </wvobject>
+         <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/eppwait" type="logic" db_ref_id="1">
+            <obj_property name="ElementShortName">eppwait</obj_property>
+            <obj_property name="ObjectShortName">eppwait</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group407" type="group">
+         <obj_property name="label">ram</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/ramcs" type="logic" db_ref_id="1">
+            <obj_property name="ElementShortName">ramcs</obj_property>
+            <obj_property name="ObjectShortName">ramcs</obj_property>
+         </wvobject>
+         <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/flashcs" type="logic" db_ref_id="1">
+            <obj_property name="ElementShortName">flashcs</obj_property>
+            <obj_property name="ObjectShortName">flashcs</obj_property>
+         </wvobject>
+         <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/memwr" type="logic" db_ref_id="1">
+            <obj_property name="ElementShortName">memwr</obj_property>
+            <obj_property name="ObjectShortName">memwr</obj_property>
+         </wvobject>
+         <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/memoe" type="logic" db_ref_id="1">
+            <obj_property name="ElementShortName">memoe</obj_property>
+            <obj_property name="ObjectShortName">memoe</obj_property>
+         </wvobject>
+         <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/ramub" type="logic" db_ref_id="1">
+            <obj_property name="ElementShortName">ramub</obj_property>
+            <obj_property name="ObjectShortName">ramub</obj_property>
+         </wvobject>
+         <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/ramlb" type="logic" db_ref_id="1">
+            <obj_property name="ElementShortName">ramlb</obj_property>
+            <obj_property name="ObjectShortName">ramlb</obj_property>
+         </wvobject>
+         <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/ramcre" type="logic" db_ref_id="1">
+            <obj_property name="ElementShortName">ramcre</obj_property>
+            <obj_property name="ObjectShortName">ramcre</obj_property>
+         </wvobject>
+         <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/ramadv" type="logic" db_ref_id="1">
+            <obj_property name="ElementShortName">ramadv</obj_property>
+            <obj_property name="ObjectShortName">ramadv</obj_property>
+         </wvobject>
+         <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/ramclk" type="logic" db_ref_id="1">
+            <obj_property name="ElementShortName">ramclk</obj_property>
+            <obj_property name="ObjectShortName">ramclk</obj_property>
+         </wvobject>
+         <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/ramwait" type="logic" db_ref_id="1">
+            <obj_property name="ElementShortName">ramwait</obj_property>
+            <obj_property name="ObjectShortName">ramwait</obj_property>
+         </wvobject>
+         <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/flashrp" type="logic" db_ref_id="1">
+            <obj_property name="ElementShortName">flashrp</obj_property>
+            <obj_property name="ObjectShortName">flashrp</obj_property>
+         </wvobject>
+         <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/flashststs" type="logic" db_ref_id="1">
+            <obj_property name="ElementShortName">flashststs</obj_property>
+            <obj_property name="ObjectShortName">flashststs</obj_property>
+         </wvobject>
+         <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/memadr" type="array" db_ref_id="1">
+            <obj_property name="ElementShortName">memadr[23:1]</obj_property>
+            <obj_property name="ObjectShortName">memadr[23:1]</obj_property>
+            <obj_property name="Radix">HEXRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/memdb" type="array" db_ref_id="1">
+            <obj_property name="ElementShortName">memdb[15:0]</obj_property>
+            <obj_property name="ObjectShortName">memdb[15:0]</obj_property>
+            <obj_property name="Radix">HEXRADIX</obj_property>
+         </wvobject>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group427" type="group">
+      <obj_property name="label">eppctrl</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instEppCtrl/clk" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">clk</obj_property>
+         <obj_property name="ObjectShortName">clk</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instEppCtrl/eppdbin" type="array" db_ref_id="1">
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="ElementShortName">eppdbin[7:0]</obj_property>
+         <obj_property name="ObjectShortName">eppdbin[7:0]</obj_property>
+         <obj_property name="label">eppdbin[7:0] - usbdb</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instEppCtrl/eppwr" type="logic" db_ref_id="1">
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="ElementShortName">eppwr</obj_property>
+         <obj_property name="ObjectShortName">eppwr</obj_property>
+         <obj_property name="label">eppwr - usbflag</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instEppCtrl/epprst" type="logic" db_ref_id="1">
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="ElementShortName">epprst</obj_property>
+         <obj_property name="ObjectShortName">epprst</obj_property>
+         <obj_property name="label">epprst - UsbMode</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instEppCtrl/eppastb" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">eppastb</obj_property>
+         <obj_property name="ObjectShortName">eppastb</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instEppCtrl/eppdstb" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">eppdstb</obj_property>
+         <obj_property name="ObjectShortName">eppdstb</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instEppCtrl/steppcur" type="other" db_ref_id="1">
+         <obj_property name="ElementShortName">steppcur</obj_property>
+         <obj_property name="ObjectShortName">steppcur</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instEppCtrl/ctleppawr" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctleppawr</obj_property>
+         <obj_property name="ObjectShortName">ctleppawr</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instEppCtrl/handshakereqin" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">handshakereqin</obj_property>
+         <obj_property name="ObjectShortName">handshakereqin</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instEppCtrl/ctleppdwrout" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctleppdwrout</obj_property>
+         <obj_property name="ObjectShortName">ctleppdwrout</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instEppCtrl/eppwait" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">eppwait</obj_property>
+         <obj_property name="ObjectShortName">eppwait</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instEppCtrl/eppdbout" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">eppdbout[7:0]</obj_property>
+         <obj_property name="ObjectShortName">eppdbout[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instEppCtrl/buseppout" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">buseppout[7:0]</obj_property>
+         <obj_property name="ObjectShortName">buseppout[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instEppCtrl/buseppin" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">buseppin[7:0]</obj_property>
+         <obj_property name="ObjectShortName">buseppin[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instEppCtrl/regeppadrout" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">regeppadrout[7:0]</obj_property>
+         <obj_property name="ObjectShortName">regeppadrout[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instEppCtrl/buseppinternal" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">buseppinternal[7:0]</obj_property>
+         <obj_property name="ObjectShortName">buseppinternal[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instEppCtrl/ctlepprdcycleout" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctlepprdcycleout</obj_property>
+         <obj_property name="ObjectShortName">ctlepprdcycleout</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instEppCtrl/ctleppdonein" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctleppdonein</obj_property>
+         <obj_property name="ObjectShortName">ctleppdonein</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instEppCtrl/ctleppstartout" type="logic" db_ref_id="1">
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="ElementShortName">ctleppstartout</obj_property>
+         <obj_property name="ObjectShortName">ctleppstartout</obj_property>
+         <obj_property name="label">ctleppstartout</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group197" type="group">
+      <obj_property name="label">memctrl</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/ctlmsmstartin" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctlmsmstartin</obj_property>
+         <obj_property name="ObjectShortName">ctlmsmstartin</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/ctlmsmdoneout" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctlmsmdoneout</obj_property>
+         <obj_property name="ObjectShortName">ctlmsmdoneout</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/ctlmcroe" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctlmcroe</obj_property>
+         <obj_property name="ObjectShortName">ctlmcroe</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/ctlmcrflashcs" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctlmcrflashcs</obj_property>
+         <obj_property name="ObjectShortName">ctlmcrflashcs</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/regmemctl" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">regmemctl[7:0]</obj_property>
+         <obj_property name="ObjectShortName">regmemctl[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/stmsmcur" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">stmsmcur[3:0]</obj_property>
+         <obj_property name="ObjectShortName">stmsmcur[3:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/stmsmnext" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">stmsmnext[3:0]</obj_property>
+         <obj_property name="ObjectShortName">stmsmnext[3:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/componentselect" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">componentselect</obj_property>
+         <obj_property name="ObjectShortName">componentselect</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/regeppadrin" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">regeppadrin[7:0]</obj_property>
+         <obj_property name="ObjectShortName">regeppadrin[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/clk" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">clk</obj_property>
+         <obj_property name="ObjectShortName">clk</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/handshakereqout" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">handshakereqout</obj_property>
+         <obj_property name="ObjectShortName">handshakereqout</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/ctlepprdcyclein" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctlepprdcyclein</obj_property>
+         <obj_property name="ObjectShortName">ctlepprdcyclein</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/ctlmsmdwrin" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctlmsmdwrin</obj_property>
+         <obj_property name="ObjectShortName">ctlmsmdwrin</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/epprddataout" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">epprddataout[7:0]</obj_property>
+         <obj_property name="ObjectShortName">epprddataout[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/eppwrdatain" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">eppwrdatain[7:0]</obj_property>
+         <obj_property name="ObjectShortName">eppwrdatain[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/memdb" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">memdb[15:0]</obj_property>
+         <obj_property name="ObjectShortName">memdb[15:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/memadr" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">memadr[23:1]</obj_property>
+         <obj_property name="ObjectShortName">memadr[23:1]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/flashbyte" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">flashbyte</obj_property>
+         <obj_property name="ObjectShortName">flashbyte</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/ramcs" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ramcs</obj_property>
+         <obj_property name="ObjectShortName">ramcs</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/flashcs" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">flashcs</obj_property>
+         <obj_property name="ObjectShortName">flashcs</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/memwr" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">memwr</obj_property>
+         <obj_property name="ObjectShortName">memwr</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/memoe" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">memoe</obj_property>
+         <obj_property name="ObjectShortName">memoe</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/ramub" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ramub</obj_property>
+         <obj_property name="ObjectShortName">ramub</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/ramlb" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ramlb</obj_property>
+         <obj_property name="ObjectShortName">ramlb</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/ramcre" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ramcre</obj_property>
+         <obj_property name="ObjectShortName">ramcre</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/ramadv" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ramadv</obj_property>
+         <obj_property name="ObjectShortName">ramadv</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/ramclk" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ramclk</obj_property>
+         <obj_property name="ObjectShortName">ramclk</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/ramwait" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ramwait</obj_property>
+         <obj_property name="ObjectShortName">ramwait</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/flashrp" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">flashrp</obj_property>
+         <obj_property name="ObjectShortName">flashrp</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/flashststs" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">flashststs</obj_property>
+         <obj_property name="ObjectShortName">flashststs</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/memctrlenabled" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">memctrlenabled</obj_property>
+         <obj_property name="ObjectShortName">memctrlenabled</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/delaycnt" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">delaycnt[4:0]</obj_property>
+         <obj_property name="ObjectShortName">delaycnt[4:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/regmemadr" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">regmemadr[23:0]</obj_property>
+         <obj_property name="ObjectShortName">regmemadr[23:0]</obj_property>
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/regmemadr" type="array" db_ref_id="1">
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="ElementShortName">regmemadr[23:0]</obj_property>
+         <obj_property name="ObjectShortName">regmemadr[23:0]</obj_property>
+         <obj_property name="label">regmemadr[23:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/carryoutl" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">carryoutl</obj_property>
+         <obj_property name="ObjectShortName">carryoutl</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/carryoutm" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">carryoutm</obj_property>
+         <obj_property name="ObjectShortName">carryoutm</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/regmemwrdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">regmemwrdata[15:0]</obj_property>
+         <obj_property name="ObjectShortName">regmemwrdata[15:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/regmemrddata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">regmemrddata[7:0]</obj_property>
+         <obj_property name="ObjectShortName">regmemrddata[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/regmemrddataaux" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">regmemrddataaux[7:0]</obj_property>
+         <obj_property name="ObjectShortName">regmemrddataaux[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/busmemin" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">busmemin[15:0]</obj_property>
+         <obj_property name="ObjectShortName">busmemin[15:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/busmemout" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">busmemout[15:0]</obj_property>
+         <obj_property name="ObjectShortName">busmemout[15:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/ctlmcroe" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctlmcroe</obj_property>
+         <obj_property name="ObjectShortName">ctlmcroe</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/ctlmcrwr" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctlmcrwr</obj_property>
+         <obj_property name="ObjectShortName">ctlmcrwr</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/ctlmcrramcs" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctlmcrramcs</obj_property>
+         <obj_property name="ObjectShortName">ctlmcrramcs</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/ctlmcrflashcs" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctlmcrflashcs</obj_property>
+         <obj_property name="ObjectShortName">ctlmcrflashcs</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/ctlmcrenable" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctlmcrenable</obj_property>
+         <obj_property name="ObjectShortName">ctlmcrenable</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/ctlmcrword" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctlmcrword</obj_property>
+         <obj_property name="ObjectShortName">ctlmcrword</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/ctlmcrdir" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctlmcrdir</obj_property>
+         <obj_property name="ObjectShortName">ctlmcrdir</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/ctlmsmoe" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctlmsmoe</obj_property>
+         <obj_property name="ObjectShortName">ctlmsmoe</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/ctlmsmwr" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctlmsmwr</obj_property>
+         <obj_property name="ObjectShortName">ctlmsmwr</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/ctlmsmramcs" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctlmsmramcs</obj_property>
+         <obj_property name="ObjectShortName">ctlmsmramcs</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/ctlmsmflashcs" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctlmsmflashcs</obj_property>
+         <obj_property name="ObjectShortName">ctlmsmflashcs</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/ctlmsmdir" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctlmsmdir</obj_property>
+         <obj_property name="ObjectShortName">ctlmsmdir</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/ctlmsmadrinc" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctlmsmadrinc</obj_property>
+         <obj_property name="ObjectShortName">ctlmsmadrinc</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/XLXI_120/ctlmsmwrcmd" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctlmsmwrcmd</obj_property>
+         <obj_property name="ObjectShortName">ctlmsmwrcmd</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group281" type="group">
+      <obj_property name="label">memtest</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/clk" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">clk</obj_property>
+         <obj_property name="ObjectShortName">clk</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/handshakereqout" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">handshakereqout</obj_property>
+         <obj_property name="ObjectShortName">handshakereqout</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/ctlmsmstartin" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctlmsmstartin</obj_property>
+         <obj_property name="ObjectShortName">ctlmsmstartin</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/ctlmsmdoneout" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctlmsmdoneout</obj_property>
+         <obj_property name="ObjectShortName">ctlmsmdoneout</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/ctlmsmdwrin" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctlmsmdwrin</obj_property>
+         <obj_property name="ObjectShortName">ctlmsmdwrin</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/ctlepprdcyclein" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctlepprdcyclein</obj_property>
+         <obj_property name="ObjectShortName">ctlepprdcyclein</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/epprddataout" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">epprddataout[7:0]</obj_property>
+         <obj_property name="ObjectShortName">epprddataout[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/eppwrdatain" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">eppwrdatain[7:0]</obj_property>
+         <obj_property name="ObjectShortName">eppwrdatain[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/regeppadrin" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">regeppadrin[7:0]</obj_property>
+         <obj_property name="ObjectShortName">regeppadrin[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/componentselect" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">componentselect</obj_property>
+         <obj_property name="ObjectShortName">componentselect</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/memdb" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">memdb[15:0]</obj_property>
+         <obj_property name="ObjectShortName">memdb[15:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/memadr" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">memadr[23:1]</obj_property>
+         <obj_property name="ObjectShortName">memadr[23:1]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/flashbyte" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">flashbyte</obj_property>
+         <obj_property name="ObjectShortName">flashbyte</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/ramcs" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ramcs</obj_property>
+         <obj_property name="ObjectShortName">ramcs</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/flashcs" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">flashcs</obj_property>
+         <obj_property name="ObjectShortName">flashcs</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/memwr" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">memwr</obj_property>
+         <obj_property name="ObjectShortName">memwr</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/memoe" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">memoe</obj_property>
+         <obj_property name="ObjectShortName">memoe</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/ramub" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ramub</obj_property>
+         <obj_property name="ObjectShortName">ramub</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/ramlb" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ramlb</obj_property>
+         <obj_property name="ObjectShortName">ramlb</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/ramcre" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ramcre</obj_property>
+         <obj_property name="ObjectShortName">ramcre</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/ramadv" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ramadv</obj_property>
+         <obj_property name="ObjectShortName">ramadv</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/ramclk" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ramclk</obj_property>
+         <obj_property name="ObjectShortName">ramclk</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/ramwait" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ramwait</obj_property>
+         <obj_property name="ObjectShortName">ramwait</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/flashrp" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">flashrp</obj_property>
+         <obj_property name="ObjectShortName">flashrp</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/flashststs" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">flashststs</obj_property>
+         <obj_property name="ObjectShortName">flashststs</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/testctrlenabled" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">testctrlenabled</obj_property>
+         <obj_property name="ObjectShortName">testctrlenabled</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/sttestcur" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">sttestcur[3:0]</obj_property>
+         <obj_property name="ObjectShortName">sttestcur[3:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/sttestnext" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">sttestnext[3:0]</obj_property>
+         <obj_property name="ObjectShortName">sttestnext[3:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/stmsmcur" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">stmsmcur[2:0]</obj_property>
+         <obj_property name="ObjectShortName">stmsmcur[2:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/stmsmnext" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">stmsmnext[2:0]</obj_property>
+         <obj_property name="ObjectShortName">stmsmnext[2:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/delaycnt" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">delaycnt[4:0]</obj_property>
+         <obj_property name="ObjectShortName">delaycnt[4:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/regmemadr" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">regmemadr[23:0]</obj_property>
+         <obj_property name="ObjectShortName">regmemadr[23:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/carryoutl" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">carryoutl</obj_property>
+         <obj_property name="ObjectShortName">carryoutl</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/carryoutm" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">carryoutm</obj_property>
+         <obj_property name="ObjectShortName">carryoutm</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/regmemwrdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">regmemwrdata[15:0]</obj_property>
+         <obj_property name="ObjectShortName">regmemwrdata[15:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/regmemrddata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">regmemrddata[15:0]</obj_property>
+         <obj_property name="ObjectShortName">regmemrddata[15:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/busmemin" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">busmemin[15:0]</obj_property>
+         <obj_property name="ObjectShortName">busmemin[15:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/busmemout" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">busmemout[15:0]</obj_property>
+         <obj_property name="ObjectShortName">busmemout[15:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/ctlmsmoe" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctlmsmoe</obj_property>
+         <obj_property name="ObjectShortName">ctlmsmoe</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/ctlmsmwr" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctlmsmwr</obj_property>
+         <obj_property name="ObjectShortName">ctlmsmwr</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/ctlmsmramcs" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctlmsmramcs</obj_property>
+         <obj_property name="ObjectShortName">ctlmsmramcs</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/ctlmsmflashcs" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctlmsmflashcs</obj_property>
+         <obj_property name="ObjectShortName">ctlmsmflashcs</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/ctlmsmdir" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctlmsmdir</obj_property>
+         <obj_property name="ObjectShortName">ctlmsmdir</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/ctlmsmwrcmd" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ctlmsmwrcmd</obj_property>
+         <obj_property name="ObjectShortName">ctlmsmwrcmd</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/flagtestrun" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">flagtestrun</obj_property>
+         <obj_property name="ObjectShortName">flagtestrun</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/flagmsmwrcycle" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">flagmsmwrcycle</obj_property>
+         <obj_property name="ObjectShortName">flagmsmwrcycle</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/flagrightcode" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">flagrightcode</obj_property>
+         <obj_property name="ObjectShortName">flagrightcode</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instNexysOnBoardMemTest/cnttimer" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">cnttimer[25:0]</obj_property>
+         <obj_property name="ObjectShortName">cnttimer[25:0]</obj_property>
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group304" type="group">
+      <obj_property name="label">blockram</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instBlockRamCtrl/usbclk" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">usbclk</obj_property>
+         <obj_property name="ObjectShortName">usbclk</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instBlockRamCtrl/usbmode" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">usbmode</obj_property>
+         <obj_property name="ObjectShortName">usbmode</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instBlockRamCtrl/usbdir" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">usbdir</obj_property>
+         <obj_property name="ObjectShortName">usbdir</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instBlockRamCtrl/usboe" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">usboe</obj_property>
+         <obj_property name="ObjectShortName">usboe</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instBlockRamCtrl/usbrd" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">usbrd</obj_property>
+         <obj_property name="ObjectShortName">usbrd</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instBlockRamCtrl/usbwr" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">usbwr</obj_property>
+         <obj_property name="ObjectShortName">usbwr</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instBlockRamCtrl/usbpktend" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">usbpktend</obj_property>
+         <obj_property name="ObjectShortName">usbpktend</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instBlockRamCtrl/usbflag" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">usbflag</obj_property>
+         <obj_property name="ObjectShortName">usbflag</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instBlockRamCtrl/usbadr" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">usbadr[1:0]</obj_property>
+         <obj_property name="ObjectShortName">usbadr[1:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instBlockRamCtrl/usbdbin" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">usbdbin[7:0]</obj_property>
+         <obj_property name="ObjectShortName">usbdbin[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instBlockRamCtrl/usbdbout" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">usbdbout[7:0]</obj_property>
+         <obj_property name="ObjectShortName">usbdbout[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instBlockRamCtrl/stream6bytes" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">stream6bytes[47:0]</obj_property>
+         <obj_property name="ObjectShortName">stream6bytes[47:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instBlockRamCtrl/state" type="other" db_ref_id="1">
+         <obj_property name="ElementShortName">state</obj_property>
+         <obj_property name="ObjectShortName">state</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instBlockRamCtrl/next_state" type="other" db_ref_id="1">
+         <obj_property name="ElementShortName">next_state</obj_property>
+         <obj_property name="ObjectShortName">next_state</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instBlockRamCtrl/streamadr" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">streamadr[14:0]</obj_property>
+         <obj_property name="ObjectShortName">streamadr[14:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instBlockRamCtrl/streamlen" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">streamlen[31:0]</obj_property>
+         <obj_property name="ObjectShortName">streamlen[31:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instBlockRamCtrl/adrcounter" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">adrcounter[14:0]</obj_property>
+         <obj_property name="ObjectShortName">adrcounter[14:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instBlockRamCtrl/bytecounter" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">bytecounter[31:0]</obj_property>
+         <obj_property name="ObjectShortName">bytecounter[31:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instBlockRamCtrl/ramdo" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">ramdo[7:0]</obj_property>
+         <obj_property name="ObjectShortName">ramdo[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instBlockRamCtrl/iusbop" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">iusbop</obj_property>
+         <obj_property name="ObjectShortName">iusbop</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instBlockRamCtrl/ramwr" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ramwr</obj_property>
+         <obj_property name="ObjectShortName">ramwr</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instBlockRamCtrl/counterzero" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">counterzero</obj_property>
+         <obj_property name="ObjectShortName">counterzero</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group399" type="group">
+      <obj_property name="label">uut</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/clk" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">clk</obj_property>
+         <obj_property name="ObjectShortName">clk</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/memadr" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">memadr[23:1]</obj_property>
+         <obj_property name="ObjectShortName">memadr[23:1]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/memdb" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">memdb[15:0]</obj_property>
+         <obj_property name="ObjectShortName">memdb[15:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/btn" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">btn[3:0]</obj_property>
+         <obj_property name="ObjectShortName">btn[3:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/eppastb" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">eppastb</obj_property>
+         <obj_property name="ObjectShortName">eppastb</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/eppdstb" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">eppdstb</obj_property>
+         <obj_property name="ObjectShortName">eppdstb</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/flashststs" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">flashststs</obj_property>
+         <obj_property name="ObjectShortName">flashststs</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/ramwait" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ramwait</obj_property>
+         <obj_property name="ObjectShortName">ramwait</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/rsrx" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">rsrx</obj_property>
+         <obj_property name="ObjectShortName">rsrx</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/sw" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">sw[7:0]</obj_property>
+         <obj_property name="ObjectShortName">sw[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/usbclk" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">usbclk</obj_property>
+         <obj_property name="ObjectShortName">usbclk</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/usbdir" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">usbdir</obj_property>
+         <obj_property name="ObjectShortName">usbdir</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/usbflag" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">usbflag</obj_property>
+         <obj_property name="ObjectShortName">usbflag</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/usbmode" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">usbmode</obj_property>
+         <obj_property name="ObjectShortName">usbmode</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/an" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">an[3:0]</obj_property>
+         <obj_property name="ObjectShortName">an[3:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/dp" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">dp</obj_property>
+         <obj_property name="ObjectShortName">dp</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/eppwait" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">eppwait</obj_property>
+         <obj_property name="ObjectShortName">eppwait</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/flashcs" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">flashcs</obj_property>
+         <obj_property name="ObjectShortName">flashcs</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/flashrp" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">flashrp</obj_property>
+         <obj_property name="ObjectShortName">flashrp</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/hsync" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">hsync</obj_property>
+         <obj_property name="ObjectShortName">hsync</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/led" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">led[7:0]</obj_property>
+         <obj_property name="ObjectShortName">led[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/memoe" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">memoe</obj_property>
+         <obj_property name="ObjectShortName">memoe</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/memwr" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">memwr</obj_property>
+         <obj_property name="ObjectShortName">memwr</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/ramadv" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ramadv</obj_property>
+         <obj_property name="ObjectShortName">ramadv</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/ramclk" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ramclk</obj_property>
+         <obj_property name="ObjectShortName">ramclk</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/ramcre" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ramcre</obj_property>
+         <obj_property name="ObjectShortName">ramcre</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/ramcs" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ramcs</obj_property>
+         <obj_property name="ObjectShortName">ramcs</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/ramlb" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ramlb</obj_property>
+         <obj_property name="ObjectShortName">ramlb</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/ramub" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ramub</obj_property>
+         <obj_property name="ObjectShortName">ramub</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/seg" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">seg[6:0]</obj_property>
+         <obj_property name="ObjectShortName">seg[6:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/usbadr" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">usbadr[1:0]</obj_property>
+         <obj_property name="ObjectShortName">usbadr[1:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/usboe" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">usboe</obj_property>
+         <obj_property name="ObjectShortName">usboe</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/usbpktend" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">usbpktend</obj_property>
+         <obj_property name="ObjectShortName">usbpktend</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/usbwr" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">usbwr</obj_property>
+         <obj_property name="ObjectShortName">usbwr</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/vgablue" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">vgablue[2:1]</obj_property>
+         <obj_property name="ObjectShortName">vgablue[2:1]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/vgagreen" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">vgagreen[2:0]</obj_property>
+         <obj_property name="ObjectShortName">vgagreen[2:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/vgared" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">vgared[2:0]</obj_property>
+         <obj_property name="ObjectShortName">vgared[2:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/vsync" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">vsync</obj_property>
+         <obj_property name="ObjectShortName">vsync</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/pio" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">pio[67:0]</obj_property>
+         <obj_property name="ObjectShortName">pio[67:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/ps2c" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ps2c</obj_property>
+         <obj_property name="ObjectShortName">ps2c</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/ps2d" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ps2d</obj_property>
+         <obj_property name="ObjectShortName">ps2d</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/rstx" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">rstx</obj_property>
+         <obj_property name="ObjectShortName">rstx</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/usbdb" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">usbdb[7:0]</obj_property>
+         <obj_property name="ObjectShortName">usbdb[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_1487" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_1487[7:0]</obj_property>
+         <obj_property name="ObjectShortName">xlxn_1487[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_1488" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_1488</obj_property>
+         <obj_property name="ObjectShortName">xlxn_1488</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_1526" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_1526[7:0]</obj_property>
+         <obj_property name="ObjectShortName">xlxn_1526[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_1527" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_1527</obj_property>
+         <obj_property name="ObjectShortName">xlxn_1527</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_1579" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_1579</obj_property>
+         <obj_property name="ObjectShortName">xlxn_1579</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_1747" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_1747[3:0]</obj_property>
+         <obj_property name="ObjectShortName">xlxn_1747[3:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_1748" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_1748[3:0]</obj_property>
+         <obj_property name="ObjectShortName">xlxn_1748[3:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_1749" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_1749[3:0]</obj_property>
+         <obj_property name="ObjectShortName">xlxn_1749[3:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_1750" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_1750</obj_property>
+         <obj_property name="ObjectShortName">xlxn_1750</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_1751" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_1751</obj_property>
+         <obj_property name="ObjectShortName">xlxn_1751</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_1848" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_1848[3:0]</obj_property>
+         <obj_property name="ObjectShortName">xlxn_1848[3:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_1849" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_1849</obj_property>
+         <obj_property name="ObjectShortName">xlxn_1849</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_1852" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_1852[6:0]</obj_property>
+         <obj_property name="ObjectShortName">xlxn_1852[6:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_1882" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_1882</obj_property>
+         <obj_property name="ObjectShortName">xlxn_1882</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_1902" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_1902</obj_property>
+         <obj_property name="ObjectShortName">xlxn_1902</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_1938" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_1938</obj_property>
+         <obj_property name="ObjectShortName">xlxn_1938</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_1939" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_1939[6:0]</obj_property>
+         <obj_property name="ObjectShortName">xlxn_1939[6:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_1940" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_1940[3:0]</obj_property>
+         <obj_property name="ObjectShortName">xlxn_1940[3:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_1944" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_1944[7:0]</obj_property>
+         <obj_property name="ObjectShortName">xlxn_1944[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_1947" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_1947</obj_property>
+         <obj_property name="ObjectShortName">xlxn_1947</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_1948" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_1948</obj_property>
+         <obj_property name="ObjectShortName">xlxn_1948</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_1949" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_1949</obj_property>
+         <obj_property name="ObjectShortName">xlxn_1949</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_2184" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_2184[7:0]</obj_property>
+         <obj_property name="ObjectShortName">xlxn_2184[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_2186" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_2186[7:0]</obj_property>
+         <obj_property name="ObjectShortName">xlxn_2186[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_2187" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_2187[7:0]</obj_property>
+         <obj_property name="ObjectShortName">xlxn_2187[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_2196" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_2196[7:0]</obj_property>
+         <obj_property name="ObjectShortName">xlxn_2196[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_2212" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_2212[47:0]</obj_property>
+         <obj_property name="ObjectShortName">xlxn_2212[47:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_2230" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_2230[7:0]</obj_property>
+         <obj_property name="ObjectShortName">xlxn_2230[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_2235" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_2235</obj_property>
+         <obj_property name="ObjectShortName">xlxn_2235</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_2236" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_2236</obj_property>
+         <obj_property name="ObjectShortName">xlxn_2236</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_2237" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_2237</obj_property>
+         <obj_property name="ObjectShortName">xlxn_2237</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_2238" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_2238</obj_property>
+         <obj_property name="ObjectShortName">xlxn_2238</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_2239" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_2239</obj_property>
+         <obj_property name="ObjectShortName">xlxn_2239</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_2252" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_2252</obj_property>
+         <obj_property name="ObjectShortName">xlxn_2252</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_2549" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_2549[7:0]</obj_property>
+         <obj_property name="ObjectShortName">xlxn_2549[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_2550" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_2550[1:0]</obj_property>
+         <obj_property name="ObjectShortName">xlxn_2550[1:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/xlxn_2570" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">xlxn_2570</obj_property>
+         <obj_property name="ObjectShortName">xlxn_2570</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/ramlb_dummy" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ramlb_dummy</obj_property>
+         <obj_property name="ObjectShortName">ramlb_dummy</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/memoe_dummy" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">memoe_dummy</obj_property>
+         <obj_property name="ObjectShortName">memoe_dummy</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/ramadv_dummy" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ramadv_dummy</obj_property>
+         <obj_property name="ObjectShortName">ramadv_dummy</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/flashrp_dummy" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">flashrp_dummy</obj_property>
+         <obj_property name="ObjectShortName">flashrp_dummy</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/ramub_dummy" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ramub_dummy</obj_property>
+         <obj_property name="ObjectShortName">ramub_dummy</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/ramcs_dummy" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ramcs_dummy</obj_property>
+         <obj_property name="ObjectShortName">ramcs_dummy</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/memwr_dummy" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">memwr_dummy</obj_property>
+         <obj_property name="ObjectShortName">memwr_dummy</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/flashcs_dummy" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">flashcs_dummy</obj_property>
+         <obj_property name="ObjectShortName">flashcs_dummy</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/memadr_dummy" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">memadr_dummy[23:1]</obj_property>
+         <obj_property name="ObjectShortName">memadr_dummy[23:1]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/ramcre_dummy" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ramcre_dummy</obj_property>
+         <obj_property name="ObjectShortName">ramcre_dummy</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/ramclk_dummy" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">ramclk_dummy</obj_property>
+         <obj_property name="ObjectShortName">ramclk_dummy</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group434" type="group">
+      <obj_property name="label">compsel</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instCompSel/regeppadrin" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">regeppadrin[7:0]</obj_property>
+         <obj_property name="ObjectShortName">regeppadrin[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instCompSel/cs80_9f" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">cs80_9f</obj_property>
+         <obj_property name="ObjectShortName">cs80_9f</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instCompSel/cs0_7" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">cs0_7</obj_property>
+         <obj_property name="ObjectShortName">cs0_7</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instCompSel/cs8_f" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">cs8_f</obj_property>
+         <obj_property name="ObjectShortName">cs8_f</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instCompSel/cs10" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">cs10</obj_property>
+         <obj_property name="ObjectShortName">cs10</obj_property>
+      </wvobject>
+      <wvobject fp_name="/demowithmemcfg_demowithmemcfg_sch_tb/UUT/instCompSel/csb0" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">csb0</obj_property>
+         <obj_property name="ObjectShortName">csb0</obj_property>
+      </wvobject>
+   </wvobject>
+</wave_config>