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Make assignments between packed LogicArrays and Logics in generated SystemVerilog avoid a swizzle #559

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mkorbel1 opened this issue Jan 29, 2025 · 0 comments
Open

Make assignments between packed LogicArrays and Logics in generated SystemVerilog avoid a swizzle #559

mkorbel1 opened this issue Jan 29, 2025 · 0 comments
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enhancement New feature or request help wanted Extra attention is needed

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@mkorbel1
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Motivation

Sometimes there are assignments between a LogicArray with 1 dimension (packed), and a Logic of the same width. It would be nice to generate that SystemVerilog as a simple assignment instead of first going through a swizzle conversion.

Desired solution

Somehow transform assignments in generated SystemVerilog to avoid unnecessary swizzling prior to assignments between 1-D packed LogicArrays and Logics.

Alternatives considered

No response

Additional details

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@mkorbel1 mkorbel1 added the enhancement New feature or request label Jan 29, 2025
@mkorbel1 mkorbel1 added the help wanted Extra attention is needed label Feb 5, 2025
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@mkorbel1